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參數(shù)資料
| 型號： | MC68HC05F4FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 73/130頁 |
| 文件大小： | 2089K |
| 代理商： | MC68HC05F4FB |
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MC68HC05F4
MOTOROLA
5-3
CORE TIMER
5
5.2
Core timer registers
5.2.1
Core timer control and status register (CTCSR)
CTOF — Core timer overow
1 (set)
–
Core timer overow has occurred.
0 (clear) –
No core timer overow interrupt has been generated.
CTOF is a read-only status bit and is set when the core timer counter register rolls over from $FF
to $00; an interrupt request will be generated if CTOFE is set. When set, CTOF may be cleared
by writing a ‘1’ to RTOF.
RTIF — Real time interrupt ag
1 (set)
–
A real time interrupt has occurred.
0 (clear) –
No real time interrupt has been generated.
RTIF is a read-only status bit and is set when the output of the chosen stage becomes active; an
interrupt request will be generated if RTIE is set. When set, the bit may be cleared by writing a ‘1’
to RRTIF. Reset also clears this bit.
CTOFE — Core timer overow enable
1 (set)
–
Core timer overow interrupt is enabled.
0 (clear) –
Core timer overow interrupt is disabled.
Setting this bit enables the core timer overow Interrupt. A CPU interrupt request will then be
generated whenever the CTOF bit becomes set and the I-bit in the CCR is clear. Clearing this bit
disables the core timer overow interrupt capability.
RTIE — Real time interrupt enable
1 (set)
–
Real time interrupt is enabled.
0 (clear) –
Real time interrupt is disabled.
Setting this bit enables the real time interrupt. A CPU interrupt request will then be generated
whenever the RTIF bit becomes set and the I-bit in the CCR is clear. Clearing this bit disables the
real time interrupt capability.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Core timer control/status (CTCSR)
$0008
CTOF
RTIF CTOFE RTIE
RTOF RRTIF
RT1
RT0
uu00 0011
TPG
43
05F4Book Page 3 Tuesday, August 5, 1997 1:10 pm
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