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參數(shù)資料
| 型號(hào)： | MC68HC05F4FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.789 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 99/130頁 |
| 文件大?。?/td> | 2089K |
| 代理商： | MC68HC05F4FB |
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MOTOROLA
7-4
MC68HC05F4
DTMF/MELODY GENERATOR
7
7.3
DMG registers
The DMG has two registers (row frequency control register and column frequency control register)
for row and column frequency selection respectively, and one register (tone control register) for
tone output control and mode selection.
7.3.1
Row and column frequency control registers
FCR4–FCR0 and FCC4–FCC0 control the frequency of the tone signals on the row and the
column paths respectively. The row and column paths are not exactly identical owing to the
presence of the high group pre-emphasis in the column path. In order to avoid the entry of the row
DTMF tone values to the column, and vice versa, the above cases are treated as illegal. The data
validator will disable all outputs when an illegal value is detected. The bit description for DTMF and
responsibility to ensure good programming practice by initialising all registers to contain legal
values for the desired function.
7.3.2
Tone control register (TNCR)
This register controls the internal conguration and tone output timing of the DTMF/melody
generator.
MS1, MS0 — Melody select for operation
The MS0 and MS1 bits control the mode of operation of the DTMF/melody generator. There are
sine wave, square wave 1, square wave 2 and square wave 3 modes. They are specied as shown
in Table 7-3.
When square wave 2 or square wave 3 mode is selected, the TNX pin is activated. The idle state
for TNX is a logic high. The nal state of the TNX pin is still dependant on the values of TGER,
TGEC (see Table 7-4), FCR and FCC bits (when illegal values are input).
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Row freq. control (FCR)
$000D
0
FCR4
FCR3
FCR2
FCR1
FCR0
undened
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Column freq. control (FCC)
$000E
0
FCC4
FCC3
FCC2
FCC1
FCC0
undened
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Tone control (TNCR)
$000F
MS1
MS0
TGER TGEC TNOE
0
0000 0000
TPG
66
05F4Book Page 4 Tuesday, August 5, 1997 1:10 pm
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