參數(shù)資料
型號: MC68HC05L25PB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52
封裝: TQFP-52
文件頁數(shù): 103/152頁
文件大?。?/td> 897K
代理商: MC68HC05L25PB
Input/Output Ports (I/O)
MC68HC05L25 Data Sheet, Rev. 3.1
54
Freescale Semiconductor
7.2.3 Port A Pullup Register
Each port A pin may have a software programmable pullup device enabled by the RCR select bits RAH
and RAL. The pullup is activated whenever the corresponding bit in the RCR is set. Since reset clears the
RCR, all pins will initialize with the pullup devices disabled. See 7.5.6 Resistor Control Register 1.
7.2.4 Port A Wired-OR Mode Register
Port A bits 0:3 configured for output pins are wired-OR mode (open drain) only. Port A bits 4:7 configured
for output pins may have software programmable wired-OR mode (open drain) output enabled by the
AWOM bit in the WOMR. Since reset clears the WOMR, the wired-OR mode is disabled on reset. See
7.2.5 Key Wakeup Interrupt (KWI)
Four key wakeup inputs (KWI0:KWI3) share pins with port A. Each key wakeup input is enabled by the
corresponding bit in the KWIEN register which resides in the option map. KWI is enabled by the KWIE bit
in the INTCR.
When a falling edge is detected at one of the enabled key wakeup inputs, the KWIF bit in the INTSR is
set and KWI is generated if
KWIE = 1. Each input has a latch which responds only to the falling edge at the pin. All input latches are
cleared at the same time by clearing the KWIF bit. See Figure 7-9.
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