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參數(shù)資料
| 型號(hào)： | MC68HC05L25PB |
| 廠(chǎng)商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁(yè)數(shù)： | 145/152頁(yè) |
| 文件大?。?/td> | 897K |
| 代理商： | MC68HC05L25PB |
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Serial Peripheral Interface
MC68HC05L25 Data Sheet, Rev. 3.1
92
Freescale Semiconductor
.
Figure 10-1. SPI Block Diagram
10.3.4 Clock Generator
The clock generator includes a 3-bit serial clock counter. The counter starts after detecting the serial clock
and halts after setting SPIF when the counter overflows.
In master mode, this block generates serial clock (SCK) when CPU writes to the data register (SPDR)
and the clock rate is selected by SPR bit in the control register (SPCR).
In slave mode, external clock from the SCK pin is used instead of master mode clock, and SPR has no
effect.
10.3.5 Others
The SPI does not use the data register of port C. Therefore, regardless of whether the SPI is used, the
data register can be read from port C.
10.3.6 Signal Description
The basic signals SDO, SDI, and SCK of SPI are described in the following paragraphs. SCK, SDO, and
SDI pins are shared with port C pins PC0, PC1, and PC2, respectively.
10.3.7 Serial Data Out (SDO)
SDO is an output pin. This pin is shared with port C pin PC1. When the SPI is enabled by SPE bit in the
SPCR, this pin becomes an output pin. When the SPE is cleared, the pin becomes PC1 and thus
becomes an input pin. The state of PC1/SDO can be read any time through PC1 data register.
When the SPI is enabled and PC1/SDO is an output, data output becomes valid at the falling edge of the
serial clock.
CONTROL LOGIC
SPSR
SPCR
SPDR
SDO
CLOCK GENERATOR
HC05 INTERNAL BUS
INTERRUPT
CONTROLS &
ADDRESS BUS
DATA BUS
SDI
0
DORD
00000
0
SPE
MSTR
SPR
ST
ART
DCOL
SPIF
DQ
CK
R
RESET
SCK
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