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| 型號(hào)： | MC68HC05L25PB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁(yè)數(shù)： | 148/152頁(yè) |
| 文件大小： | 897K |
| 代理商： | MC68HC05L25PB |
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Register Description
MC68HC05L25 Data Sheet, Rev. 3.1
Freescale Semiconductor
95
Bits 3:1 — Reserved
These bits are reserved and always read as zero.
SPR — SPI Clock Rate Select
This is the clock rate selection bit. When set, the master mode SCK rate is the system clock divided
by 16. When clear, the rate system clock is divided by two. Reset clears this bit.
1 = System clock divided by 16
0 = System clock divided by 2
10.5.2 Serial Peripheral Status Register
SPIF — Serial Transfer Complete Flag
SPIF (serial peripheral interface flag) notifies the user that the data transfer between MC68HC05L25
and the external device has been completed. Upon completion of the data transfer, the rising edge of
the eighth serial clock pulse sets SPIF. If SPIE in the SPCR is set, the SPI interrupt (SPII) will be
generated.
While SPIF is set, all access to the SPDR is inhibited until SPSR is read by the CPU. Also, even if the
ninth serial clock is detected, the shift register (SPDR) will not operate.
Clearing the SPIF is accomplished by a software sequence of accessing the SPSR while SPIF is set
and followed by the SPDR access. (SPIF and DCOL can be cleared simultaneously.)
Reset clears this bit.
1 = Serial data transfer complete
0 = Serial data transfer in progress
DCOL — Data Collision
DCOL (data collision) notifies the user that an invalid access to the SPDR has been made. This bit is
set when an attempt was made to read or write to SPDR while a data transfer was taking place with
an external device. When DCOL is set, access to the SPDR becomes invalid. The transfer continues
uninterrupted without any effect from the SPDR access. This flag does not generate SPI interrupt. It is
read-only.
DCOL is cleared by reading the SPSR with SPIF set followed by a read or write to the SPDR. If the
last part of the clearing sequence is done after another transmission has started, DCOL will be set
again. (DCOL and SPIF can be cleared simultaneously.)
Reset clears this bit.
1 = Data collision occurred
0 = Data collision did not occur
Bits 5–0 — Reserved
These bits are unused and always read as zero.
Address:
$000B
Bit 7
654321
Bit 0
Read:
SPIF
DCOL
000000
Write:
Reset:
00000000
= Unimplemented
Figure 10-3. SPI Status Register (SPSR)
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