參數(shù)資料
型號： MC68HC05L25PB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52
封裝： TQFP-52
文件頁數(shù)： 94/152頁
文件大?。?/td> 897K
代理商： MC68HC05L25PB
Interrupts
MC68HC05L25 Data Sheet, Rev. 3.1
46
Freescale Semiconductor
6.7 Serial Peripheral Interface Interrupt (SPII)
The SPII is generated by the serial peripheral interface system at the end of one byte of data transmission
or reception. The I bit in the CCR must be clear and the SPIE bit of SPCR must be set for the SPII to be
generated. This interrupt will vector to the interrupt service routine located at the address specified by the
contents of memory locations $1FF2 and $1FF3. See Chapter 10 Serial Peripheral Interface for more
information.
6.8 Event Counter Interrupt (EVI)
The EVI interrupt is generated by the event counter system. The I bit in the CCR must be clear for the EVI
interrupt to be enabled. This interrupt will vector to the interrupt service routine located at the address
specified by the contents of memory locations $1FF4 and $1FF5. See Chapter 13 Event Counter for more
information.
6.9 Time Base Interrupt (TBI)
The TBI is generated periodically by the time base system. The I bit in the CCR must be clear for the TBI
to be enabled. This interrupt will vector to the interrupt service routine located at the address specified by
the contents of memory locations $1FF0:$1FF1. See Chapter 9 Time Base for more information.
6.10 Key Wakeup Interrupt (KWI)
The KWI interrupt is generated by the key wakeup system. The I bit in the CCR must be clear for the KWI
interrupt to be enabled. This interrupt will vector to the interrupt service routine located at the address
specified by the contents of memory locations $1FF8 and $1FF9. See Chapter 7 Input/Output Ports (I/O)
for more information.
6.11 IRQ/KWI Software Consideration
IRQ and KWI interrupts have a timing delay in a case as shown in Figure 6-5. This section shows
programming for proper interrupts with IRQ or KWI.
Figure 6-4 shows an example of a timer interrupt. In this case, the interrupt by TOF occurs as soon as
TOIE (timer overflow interrupt enable) bit is set.
Figure 6-4. Timer Interrupt
CLI
BSET TOIE, TCR
LDA
#$55
.
TOF Interrupt pending
Interrupt occurs before this instruction
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