- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄69026 > MC68HC05L25PB (FREESCALE SEMICONDUCTOR INC) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52 PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68HC05L25PB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁(yè)數(shù)： | 26/152頁(yè) |
| 文件大小： | 897K |
| 代理商： | MC68HC05L25PB |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)當(dāng)前第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)
Event Counter Interrupts
MC68HC05L25 Data Sheet, Rev. 3.1
Freescale Semiconductor
121
on the fourth internal processor clock cycle of the write to the event counter timing register. The event
counter data registers are cleared on the rising edge of the internal gate signal. The external gate signal
rises two clock cycles later.
After MT3–MT0 x tgt, the gate signal will rise, terminating the measurement time. The gate signal will be
the same length for all successive measurements.
Unless the start of the gate delay signal and the event counter input signal are externally synchronized,
the value of the least significant bit of the event counter data low register may arbitrarily change.
If the fast oscillator, OSC, is disabled, the event counter will not function properly.
13.5 Event Counter Interrupts
The event counter complete interrupt (ECCI) is generated at the falling edge of the gate signal. This
interrupt indicates the presence of valid data in the event counter data registers. Since reading the data
registers during the measurement time may give invalid results, the CPU must read the data registers
before the rising edge of the gate signal. The event counter complete interrupt can be cleared by writing
a one to RCCF. The event counter complete interrupt is cleared automatically at the beginning of each
measurement.
The event counter overflow interrupt (EVOF) is generated if the count exceeds 65,535, the maximum
value of the 16-bit event counter. This interrupt can be used to indicate an invalid measurement or to
increase the resolution of the event counter, which will be described later. The event counter overflow
interrupt can be cleared by writing a one to ROIF. The event counter overflow interrupt is cleared
automatically at the beginning of each measurement.
If an overflow occurs (the counter increments beyond $FFFF), the event counter overflow flag (EVOF) will
be set. If EVOE is set, an interrupt will be generated. Following an overflow, the event counter will
increment from zero.
The resolution of the event counter can be increased by using the event counter overflow interrupt. If it is
a count of more than 65,535 the maximum value of the 16-bit event counter is encountered, the event
counter overflow interrupt service routine should note the number of “roll-overs” that occur. The overflow
interrupt service routine should not clear the event counter interrupt. In this way, the user can be assured
that the correct count has been recorded.
13.6 Event Counter During Wait Mode
The event counter continues to operate in wait mode. If EVOE is set and an event counter overflow
interrupt occurs, the processor will exit wait mode. If EVIE is set and an event counter interrupt occurs,
the processor will exit wait mode.
13.7 Event Counter During Stop Mode
In stop mode, the event counter is disabled.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC05LJ5P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP16 |
| MC68HC05M4CFN | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC52 |
| MC68HC05M4MFN | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQCC52 |
| MC68HC05P1ADWR2 | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO28 |
| MC68HSC05P1ADWR2 | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05L28 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit |
| MC68HC05L28B | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:Flexible general-purpose microcomputer |
| MC68HC05L2B | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit |
| MC68HC05L2CB | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit |
| MC68HC05L6 | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:8-Bit Microcomputer with Liquid Crystal Driver Circuitry |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。