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參數(shù)資料
| 型號： | MC68HC58DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 34/102頁 |
| 文件大?。?/td> | 700K |
| 代理商： | MC68HC58DW |
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MC68HC58
J1850 FRAME FORMAT
MOTOROLA
TECHNICAL DATA
3-3
3.1.2.1 Logic Zero
A logic zero is defined as either an active to passive transition followed by a passive
period 64
s in length, or a passive to active transition followed by an active period 128
s in length. Refer to Figure 3-3 (A).
3.1.2.2 Logic One
A logic one is defined as either an active to passive transition followed by a passive
period 128
s in length, or a passive to active transition followed by an active period
64
s in length. Refer to Figure 3-3 (B).
3.1.3 CRC — Cyclical Redundancy Check Byte
The CRC byte is used by the receiver(s) of each frame to determine if any errors have
occurred during the transmission of the frame. The DLC calculates the CRC byte and
appends it onto any frames transmitted onto the J1850 bus, and also performs CRC
detection on any frames it receives from the J1850 bus.
CRC generation uses the divisor polynomial X8+X4+X3+X2+1. The remainder polyno-
mial is initially set to all ones, and then each byte in the frame after the SOF symbol is
serially processed through the CRC generation circuitry. The one’s complement of the
remainder then becomes the 8-bit CRC byte, which is appended to the frame after the
data bytes, in MSB to LSB order.
When receiving a frame, the DLC uses the same divisor polynomial. All data bytes,
excluding the SOF and EOD symbols, but including the CRC byte, are used to check
the CRC. If the frame is error free, the remainder polynomial equals X7+X6+X2 ($C4),
regardless of the data contained in the frame. If the calculated CRC does not equal
$C4, the DLC informs the CPU of the failure.
3.1.4 EOD — End of Data Symbol
The EOD symbol is a passive period on the J1850 bus used to signify to any recipients
of a frame that the transmission by the originator has been completed.
The EOD symbol is defined as an active to passive transition followed by a passive
period 200
s in length. Refer to Figure 3-3 (D and E).
3.1.5 NB — Normalization Bit
The NB is used to preface the in-frame response (IFR). The NB ensures that the end
of the eighth bit of the IFR always returns the bus to the passive level. The length of
the NB may be used to signify the type of IFR being used. The NB is transmitted by
the node responding to the frame, and it defines the start of the optional response seg-
ment, if utilized, of any VPW format frame. The DLC indicates that the IFR being trans-
mitted has a CRC appended by using a logic one (active short) bit. The DLC indicates
that it does not contain a CRC by using a logic zero (active long) bit.
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