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參數(shù)資料
| 型號： | MC68HC58DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 46/102頁 |
| 文件大?。?/td> | 700K |
| 代理商： | MC68HC58DW |
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MOTOROLA
DATA LINK CONTROLLER OPERATION
MC68HC58
4-4
TECHNICAL DATA
The data link controller exchanges information in pairs of bytes in both the serial and
parallel modes. A standard exchange consists of one status byte and one data byte
sent from the DLC to the host, and one data byte and one command byte sent from
the host to the DLC. In serial mode, the host and the DLC exchange pairs of bytes
simultaneously, while exchanges in parallel mode are sequential. A host can write
contiguous data bytes to the DLC in parallel mode without intervening command
bytes, provided the first and last data bytes are accompanied by “l(fā)oad as first byte of
transmit data”, “l(fā)oad as last byte of transmit data”, or “l(fā)oad as first and last byte of
transmit data” command bytes.
Data that the DLC receives from the host can be data for transmission on the SAE
J1850 bus, a configuration byte, or a null byte. The destination of a byte written to a
DLC is specified in the command byte that accompanies it. Command bytes can also
contain DLC receive, transmit, and mode control instructions.
The status byte that the host receives from the DLC contains information about the ac-
companying data byte, current status of the transmitter, and current status of the re-
ceiver. The data byte can contain received frame data, a transmission completion
code, or invalid information.
The DLC must be configured after power-up or reset, and at appropriate intervals
thereafter. To configure a DLC, the host MCU sends a configuration command byte
followed by a configuration data byte. Mode of operation, clock speed, and interrupt
mode are determined by the content of the configuration byte.
When the CS signal is asserted, interface lines (parallel or serial) are enabled, then
status and data words are prepared for transfer to the host. Parallel transfers are
controlled by the ADDR0, CLK, and R/W signals. Serial transfers are clocked by the
SCLK signal. When CS is released, interface lines are disabled and go to a high-im-
pedance state.
When interrupts are enabled, the DLC generates an interrupt based on four, or option-
ally five interrupt sources. When one of these interrupt conditions occurs, the DLC as-
serts the INT output to request service from the host. The INT output is negated when
CS is asserted by the host and the status byte is read. Refer to 4.2.3 Interrupt Re-
quests for more information.
Figure 4-3 shows typical DLC operation.
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