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參數(shù)資料
| 型號： | MC68HC58DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁數(shù)： | 45/102頁 |
| 文件大?。?/td> | 700K |
| 代理商： | MC68HC58DW |
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MC68HC58
DATA LINK CONTROLLER OPERATION
MOTOROLA
TECHNICAL DATA
4-3
4X mode allows communication on the multiplex bus to be performed at four times the
normal bit rate.
This high speed transfer function does not work properly unless all transmitting nodes
on the J1850 bus are in 4X mode. Selected receivers may be configured to ignore high
speed frames until a BREAK symbol is received. Detection of a BREAK symbol on the
J1850 bus returns the DLC to normal mode.
Refer to 4.6 BREAK Operation for more information.
4.1.6 Block Mode
Block mode is entered when the host fills the transmit first in/first out (TxFIFO) buffer
without indicating the last byte of a message.
During block mode, the terminate auto retry function is automatically enabled. The
DLC continues to transmit message bytes as long as the host loads message bytes
into the TxFIFO buffer without sending the DLC a “l(fā)oad as last byte of transmit data”
command.
The receive first in/first out (RxFIFO) buffer is designed to allow the reception of block
mode messages automatically.
Refer to 4.5 Block Mode Operation for information.
4.2 Host Interface
Figure 4-2 shows typical usage of a DLC with an MCU.
Figure 4-2 DLC Usage
DLC USAGE
RL
CL
MCU
SPI
OR
PARALLEL
DLC
LOAD
BUS
SAE J1850
BUS
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