參數(shù)資料
型號： MC68HC58DW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 75/102頁
文件大?。?/td> 700K
代理商： MC68HC58DW
MOTOROLA
CONTROL AND STATUS CODES
MC68HC58
5-8
TECHNICAL DATA
5.2.4 IMOD — Interrupt Mode Bit
The IMOD bit controls an additional interrupt source to the default interrupt sources.
When IMOD is set, an interrupt request is made when a data byte is received into an
empty RxFIFO buffer. Subsequent bytes do not cause an interrupt request unless the
RxFIFO is emptied before they are received.
0 = Default interrupts are the only ones enabled
1 = Additional interrupt source added to default sources
5.2.5 OSCD[2:1] — Oscillator Divisor Field
The OSCD bit field determines DLC internal clock frequency. The DLC internal clock
frequency is derived from a combination of the external clock frequency and the OSCD
value. Table 5-4 shows frequency division factors and the internal clock frequency
with various references. A 2 MHz internal clock frequency is required for normal oper-
ation.
5.2.6 4X — High-Speed Control Bit
Setting this bit places the DLC in high-speed data transfer mode. J1850 bus wave-
shaping is disabled.
0 = Normal clock division
1 = Four times normal clock speed
5.3 Status Byte
The status byte register conveys information about data and shows the condition of
the DLC at the time of receipt. Results of commands that are in progress may not be
reflected in the status byte until the command is completely executed.
For a DLC operating in parallel mode, the host MCU can read the status byte alone,
and a subsequent data read automatically flushes the data byte from the buffer.
For a DLC operating in SPI mode, status bytes and received data are transferred to
the host MCU in pairs. When the host reads received data, it remains in the RxFIFO
buffer until a flush command is given. The flush command can accompany the read
command. The DLC does not report the status of an action caused by the current
transfer.
Table 5-4 Internal Clock Frequency Derivations
OSCD
Clock
External Clock
Value
Divisor
2 MHz
4 MHz
6 MHz
8 MHz
00
1
2 MHz
4 MHz
6 MHz
8 MHz
01
2
1 MHz
2 MHz
3 MHz
4 MHz
10
3
0.66 MHz
1.33 MHz
2 MHz
2.66 MHz
11
4
500 kHz
1 MHz
1.5 MHz
2 MHz
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