參數(shù)資料
型號: MC68HC58DW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 66/102頁
文件大小: 700K
代理商: MC68HC58DW
MOTOROLA
DATA LINK CONTROLLER OPERATION
MC68HC58
4-22
TECHNICAL DATA
The IFR bit in the completion code byte indicates whether the associated frame in the
RxFIFO buffer is an IFR. When an IFR has been sent, the RxFIFO buffer contains the
initial frame, with completion code, plus the IFR and its completion code. The host
MCU must check the completion codes to determine that an IFR has been received.
An IFR starts with a normalization (NB) bit. This bit signals whether the IFR was
queued by a “send IFR on EOD without CRC” command (NB = 0), or by a “send IFR
on EOD with CRC command” (NB = 1). The “in-frame response” command (IFRC) bit
in the completion code byte also indicates whether a CRC byte is appended to the IFR.
The host MCU must monitor the IFRC if error checking is to be used. Due to zero-dom-
inance, J1850 bus arbitration between an IFR without CRC and an IFR with CRC is
won by an IFR without CRC.
NOTE
A DLC cannot transmit an IFR to a message it is transmitting.
Table 4-4 shows IFR error conditions. When errors are detected during an IFR, the
IFR is terminated. A completion code indicating that the frame was an IFR and that an
error occurred is placed in the RxFIFO buffer.
Table 4-4 IFR Error Conditions
Condition
Action Taken
Error in frame requiring response
Transmitter reset, TxFIFO buffer flushed (no IFR sent)
IFR loses arbitration
Transmission halts, TxFIFO buffer flushed (no IFR sent)
TxFIFO buffer underrun
CRC complemented on truncated IFR
Error in IFR during transmission
Transmission halts, transmitter reset, TxFIFO buffer flushed
J1850 bus idle when IFR loaded
Transmitter reset, TxFIFO buffer flushed
IFR loaded after EOD
Transmitter reset, TxFIFO buffer flushed
IFR loaded without first byte
Transmitter reset, TxFIFO buffer flushed
IFR command, no data
Transmitter reset, TxFIFO buffer flushed
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