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參數(shù)資料
| 型號(hào)： | MC68HC58DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PDSO28 |
| 封裝： | SOIC-28 |
| 文件頁(yè)數(shù)： | 57/102頁(yè) |
| 文件大?。?/td> | 700K |
| 代理商： | MC68HC58DW |
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MOTOROLA
DATA LINK CONTROLLER OPERATION
MC68HC58
4-14
TECHNICAL DATA
Figure 4-9 Host/DLC Serial Mode Transmit Routine (Part 1 of 2)
START TX DATA ROUTINE
LOAD FIRST BYTE OF MESSAGE TO
IS SPI TRANSFER COMPLETE?
NO
RETRIEVE THE STATUS BYTE RECEIVED
FROM THE DLC FROM SPI DATA REGISTER
YES
A
DLC HOST TRANS FLOW 1
B
LOAD “LOAD AS TRANSMIT DATA BYTE”
NEGATE DLC CS
ASSERT DLC CS
BE TRANSMITTED INTO SPI DATA
REGISTER, INITIATING SPI
TRANSFER
NO
YES
IS TX FIFO STATUS
CORRECT?
E
LOAD “LOAD AS FIRST BYTE OF TRANSMIT
DATA” COMMAND BYTE BIT COMBINATION
INTO SPI DATA REGISTER, INITIATING
SPI TRANSFER
A
IS SPI TRANSFER COMPLETE?
YES
RETRIEVE THE DATA BYTE RECEIVED
FROM THE DLC FROM SPI DATA REGISTER
AND DISCARD
NEGATE DLC CS
MINIMUM 2.5
S DELAY BETWEEN
RETRIEVE THE STATUS BYTE
RECEIVED FROM THE DLC FROM
SPI DATA REGISTER
NO
NEGATION AND ASSERTION OF CS
LOAD NEXT BYTE OF MESSAGE TO BE
TRANSMITTED INTO SPI DATA REGISTER,
INITIATING SPI TRANSFER
IS SPI TRANSFER COMPLETE?
NO
YES
B
NO
YES
IS TX FIFO STATUS
CORRECT?
E
COMMAND BYTE BIT COMBINATION
INTO SPI DATA REGISTER, INITIATING
SPI TRANSFER
IS SPI TRANSFER COMPLETE?
NO
YES
ONE BYTE LEFT IN MESSAGE?
C
NO
YES
ASSERT DLC CS
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