參數(shù)資料
型號(hào)： MC68HC58DW
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PDSO28
封裝： SOIC-28
文件頁(yè)數(shù)： 35/102頁(yè)
文件大?。?/td> 700K
代理商： MC68HC58DW
MOTOROLA
J1850 FRAME FORMAT
MC68HC58
3-4
TECHNICAL DATA
NOTE
This method of CRC recognition is the reverse of the method pre-
ferred by the SAE J1850.
3.1.6 IFR — In-Frame Response Bytes
A number of options are available in the IFR section of the J1850 frame format. The
DLC can send an IFR consisting of one or more bytes, which may be followed by a
CRC byte.
3.1.7 EOF — End of Frame Symbol
The EOF symbol is a passive period on the J1850 bus, longer than an EOD symbol,
which signifies the end of a frame. Since an EOF symbol is longer than an EOD sym-
bol, if no response is transmitted after an EOD symbol, it becomes an EOF, and the
frame is assumed to be completed.
The EOF symbol is defined as an active to passive transition followed by a passive
period of at least 280
s in length. Refer to Figure 3-3 (E). If there is no IFR byte trans-
mitted after an EOD symbol is transmitted, after another 80
s the EOD becomes an
EOF, indicating the completion of the frame.
3.1.8 IFS — Inter-Frame Separation Symbol
The IFS symbol is a passive period on the J1850 bus which allows proper synchroni-
zation between nodes during continuous frame transmission. The IFS symbol is trans-
mitted by a node following the completion of the EOF period.
When the last byte of a frame has been transmitted onto the J1850 bus, and the EOF
symbol time has expired, all nodes must then wait for the IFS symbol time to expire
before transmitting an SOF, marking the beginning of another frame.
However, if the DLC is waiting for the IFS period to expire before beginning a trans-
mission and a passive to active level is detected before the IFS time has expired, it
must internally synchronize to that edge. A passive to active level may occur during
the IFS period because of varying clock tolerances and loading of the J1850 bus,
causing different nodes to observe the completion of the IFS period at different times.
Receivers must synchronize to any SOF occurring during an IFS period to allow for
individual clock tolerances.
The IFS symbol is defined as an active to passive transition followed by a passive
period 300
s in length. Refer to Figure 3-3 (E).
3.1.9 BREAK — Break
Any DLC transmitting at the time a BREAK symbol is detected halts transmission im-
mediately, and indicates to the host MCU that a BREAK was detected. The DLC can
also transmit a BREAK symbol if necessary.
The BREAK signal is defined as a passive to active transition followed by an active
period of at least 239
s. Refer to Figure 3-3 (F).
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