MOTOROLA
SIGNAL AND PIN DESCRIPTIONS
MC68HC58
2-2
TECHNICAL DATA
2.1.1 DLC Parallel Mode Pin Function
Table 2-1 summarizes DLC pin functions when operating in parallel mode. Detailed
TERISTICS for more information on electrical specifications.
2.1.1.1 ADDR0 — Address Bit
This pin is used in conjunction with the R/W signal to address the DLC in the MCU
memory map. Although the name ADDR0 implies that the pin should be connected to
address line 0, it can in fact be connected to any address line to place it at a desired
location in memory.
2.1.1.2 BUS — SAE J1850 Multiplex Bus
This pin connects the DLC to the SAE J1850 multiplex bus. The bus signal is driven
to a nominal 7 Vdc with respect to the bus load when in an active level; it is grounded
through the bus load when in a passive level.
2.1.1.3 CS — DLC Chip-Select
This pin is used to input the DLC parallel data exchange enable signal. It has a nominal
15 k
internal pull-up resistor.
Table 2-1 MC68HC58 DLC Parallel Mode Pin Function
Name
Type
Function
ADDR0
Input
Address select signal
BUS
Input/Output
Serial data signal
CS
Input
DLC chip-select signal
DATA[7:0]
Input/Output
Bidirectional three-state data bus
ECLK
Input
6800 bus clock
INT
Output
DLC interrupt request
LITO
Input/Output
Logic in transceiver out
LOAD
Input
External bus load connection
LOTI
Input/Output
Logic out transceiver in
OSC1
Input
External clock connection
OSC2
Output
External reference connection
PSEN
Output
Power supply status signal
PRLMD
Input
Parallel/serial mode select signal
REXT
Input
Transceiver biasing resistor
RST
Input
DLC reset signal
R/W
Input
DLC data transfer control
V
BATT
Power supply
Transceiver power connection
V
CC
Power supply
Analog power connection
V
DD
Power supply
Digital power connection
V
SSA
Power supply
Analog ground
V
SSD
Power supply
Digital ground