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參數資料
| 型號： | MC68HC58FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數： | 8/102頁 |
| 文件大?。?/td> | 700K |
| 代理商： | MC68HC58FN |
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MC68HC58
INTRODUCTION
MOTOROLA
TECHNICAL DATA
1-1
SECTION 1INTRODUCTION
The MC68HC58 DLC (data link controller) handles microcontroller unit (MCU) to
Society of Automotive Engineers (SAE) J1850 bus interface duties. The MC68HC58
DLC is the successor to the MC68HC56 DLCP (data link controller parallel) and the
MC68HC57 DLCS (data link controller serial). The MC68HC58 is pin configurable to
communicate with a host MCU via an 8-bit non-multiplexed parallel data bus or a
Motorola serial peripheral interface.
The DLC consists of control logic and bus transceiver circuits. Figure 1-1 shows the
internal structure of a DLC configured for parallel mode. Figure 1-2 shows the internal
structure of a DLC configured for serial mode. The built-in bus transceiver allows the
DLC to be directly connected to the J1850 bus, thus providing a complete link between
the central processing unit (CPU) host application and the J1850 bus. The J1850 bus
protocol is a method of information transfer via messages (frames) between nodes. A
node is any location on the J1850 bus that sends and receives messages.
The following are primary features of the DLC:
SAE J1850 compatible
Class 2 (vehicle bus communication protocol) compatible
Handles all network protocol functions (access, arbitration, error detection)
Supports polled or interrupt host DLC servicing
Message buffering on transmit and receive
On-board transceiver with waveshaping
Operates with up to a 2-volt ground offset between network nodes
Pin configurable SPI or parallel host interface
Digitally filtered receiver
Host configurable oscillator divisor
Power conserving sleep feature with fast wakeup on bus or host activity
High voltage CMOS (40 volt HVCMOS) process
Built-in transient and ESD protection
The DLC handles SAE J1850 frames with minimal MCU servicing. Each DLC can be
operated in either interrupt mode or polled mode. Internal first in/first out (FIFO)
buffers, 20 bytes for receiver data and 11 bytes for transmitter data, allow full frame
length operations. The MCU typically transfers complete frames to the DLC for
transmission on the SAE J1850 bus, and is interrupted only when a complete frame is
received from the SAE J1850 bus. The DLC handles all arbitration, error detection,
and optional in-frame response duties internally.
Changes to the operating configuration can be made at any time. Depending upon the
command, the changes can be made immediately or following the current J1850 bus
transaction.
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