參數(shù)資料
型號： MC68HC58FN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC28
封裝： PLASTIC, LCC-28
文件頁數(shù)： 65/102頁
文件大小： 700K
代理商： MC68HC58FN
MC68HC58
DATA LINK CONTROLLER OPERATION
MOTOROLA
TECHNICAL DATA
4-21
If the “l(fā)oad as first byte of transmit data” command is latched while the TxFIFO buffer
is full during a block mode transfer, the data byte is not loaded and is lost.
If the “l(fā)oad as first and last byte of transmit data” command is latched while the TxFIFO
buffer is full during a block mode transfer, the data byte is not loaded and is lost.
4.6 BREAK Operation
A BREAK symbol on the J1850 bus causes any frame currently on the J1850 bus to
be corrupted. The host MCU may command a DLC to send a BREAK symbol. The
symbol starts as soon as the command byte is latched.
When a DLC receiver (including any DLC that sends the symbol) detects BREAK on
the J1850 bus, it places a completion code in the RxFIFO buffer which indicates that
the BREAK was detected. If interrupts are enabled, INT is also asserted. If a frame is
being transmitted when the BREAK is detected, the transmitter halts.
Since a BREAK symbol will cause all frames on the J1850 bus to be corrupted, if the
DLC is attempting to transmit when the BREAK is detected, it will attempt to retransmit
once an IDLE bus condition is detected following the BREAK, unless automatic retry
is disabled.
4.7 In-Frame Response (IFR)
The SAE Standard J1850 allows for an optional IFR. A frame on the J1850 bus is de-
termined to be ready for response when an EOD period has elapsed. If a reply to the
frame is initiated before the EOF period also elapses, it is designated as an IFR. IFR
transmissions are subject to the same arbitration as regular frames, but automatic re-
try is disabled during an IFR.
If the host wishes to send an IFR, a “send IFR on EOD” command byte accompanies
the first byte of an IFR. This command flushes the TxFIFO buffer and queues the IFR.
When the DLC receiver detects an EOD, the IFR is sent, provided the following con-
ditions are met:
There are no errors in the frame requiring response.
The IFR is loaded into the TxFIFO buffer after the SOF of the frame requiring re-
sponse is recognized, but before EOD is detected.
The first byte of the IFR is accompanied by either a “l(fā)oad as first byte of transmit
data” command or “l(fā)oad as first and last byte of transmit data” command.
If these conditions are satisfied, the DLC begins IFR transmission when EOD occurs.
If there is no last byte in the TxFIFO buffer when transmission begins, transmission
follows normal block-mode rules.
When the “send IFR on EOD” command flushes the TxFIFO buffer, the host MCU
must reload and resend frames that are in the TxFIFO buffer when an IFR is queued,
even when an IFR is not loaded successfully or loses arbitration.
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