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參數(shù)資料
| 型號： | MC68HC58FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 18/102頁 |
| 文件大?。?/td> | 700K |
| 代理商： | MC68HC58FN |
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MOTOROLA
SIGNAL AND PIN DESCRIPTIONS
MC68HC58
2-6
TECHNICAL DATA
The following additional guidelines apply to Figure 2-2:
1. Pull-up resistor values depend on electrical characteristics of the host MCU.
2. Exact values for the external components are a function of printed circuit board
(PCB) capacitance and inductance, socket capacitance, operating voltage and
crystal technology.
3. The example ceramic resonator is a Murata CSA4.00MGA with typical load ca-
pacitance. The DLC contains an internal 1 M
resistor across OSC1 and
OSC2. No external resistor is required.
4. L1 is a surface mount inductor which should have characteristics similar to TDK
NL322522T-470J-3.
5. The external bias resistor (REXT) determines the waveshape of J1850 bus sig-
nals transmitted by the DLC.
6. For maximum noise immunity, V
CC and VDD should be supplied by separate
lines; V
SSA and VSSD should also be separate. The VBATT pin is shown at-
tached to the permanent “unswitched” battery supply to take advantage of the
better transient protection found on this circuit rather than the “switched” bat-
tery, or ignition.
7. Applications whose requirements for electro-static discharge (ESD) protection
exceed the level provided by the bus pin internal circuitry and the bus loading
components may require additional transient protection. The example in Figure
2-2 illustrates this by including two 16 volt zener diodes placed between the bus
and ground. These diodes (part # P4SMA16AT3) should be located as close to
the module connector as possible. Refer to APPENDIX A ELECTRICAL
CHARACTERISTICS for information on maximum voltage ratings.
8. One J1850 node in the vehicle typically has a heavier BUS to LOAD pin loading.
This allows a smaller differential between the total network load of two nodes
versus 32 nodes. If 26 nodes or more are used, the heavier loading should not
be present as this may violate the maximum capacitance and minimum resis-
tance allowed by the J1850. A network of 26 or more nodes should all have the
lower load values.
9. Figure 2-2 reflects a configuration for no wake-up upon the detection of J1850
bus activity. If system wake-up upon the detection of J1850 bus activity is de-
sired, perform the following:
Tie the VDD pin to a 5 Vdc power supply. This 5 Vdc power supply is powered
down when the DLC is placed in the standby mode.
Tie the PSEN pin on the DLC through a 33 k
resistor to the ignition input of
the power supply/regulator. This limits the current sourced by the DLC. This
resistor value should be determined by the individual application. A 10 k
pull-down resistor should be included from the PSEN line to ground. A 100 k
resistor from the RST pin to ground should also be added.
Tie the VCC pin and the pull-up points for the external bias resistor (REXT) on
the DLC to a separate 5 Vdc power supply. This 5 Vdc power supply remains
powered up when the rest of the node is powered down.
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