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參數資料
| 型號： | MC68HC58FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數： | 47/102頁 |
| 文件大?。?/td> | 700K |
| 代理商： | MC68HC58FN |
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MC68HC58
DATA LINK CONTROLLER OPERATION
MOTOROLA
TECHNICAL DATA
4-5
Figure 4-3 DLC Operation
The host MCU can put a DLC in standby mode by sending it the “enter standby mode”
command byte. The DLC completes all current frames, then goes inactive. PSEN
sources VBATT while the DLC is active and goes to a high-impedance state during
standby mode. An incoming bus frame, or the host MCU asserting CS and reading the
status byte, can reactivate a DLC.
4.2.1 MC68HC58 DLC Parallel Mode Host MCU Interface
The DLC interface is designed to work with an M6800 bus clock signal (CLK), but
functions equally well with any host MCU that meets timing requirements. Refer to AP-
PENDIX A ELECTRICAL CHARACTERISTICS for more parallel host interface timing
information.
4.2.1.1 Parallel Mode Data Transfer
Parallel mode transfers are controlled by the R/W and ADDR0 signals from the host
MCU. R/W and ADDR0 determine which of four possible bytes are being transferred.
Figure 4-4 shows the parallel mode byte format.
HOST
INTERFACE
HOST INTERFACE ACTIVITY TO
TRANSFER MESSAGE INTO DLC
FOR TRANSMISSION
HOST INTERFACE ACTIVITY TO
TRANSFER RECEIVED MESSAGE
OUT OF DLC
LAST BYTE OF MESSAGE AND
COMPLETION CODE PLACED
IN RXFIFO INTERRUPT ASSERTED
BUS
INTERRUPT
LINE INT
BYTES TRANSMITTED,
MESSAGE ON BUS
INTERRUPT
CLEARED BY CS
AND STATUS READ
CS
HOST INTERFACE
ACTIVITY
BUS ACTIVITY
DLC OPERATION
RECEIVED, AND PLACED
INTO RXFIFO
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