參數(shù)資料
型號(hào)： MC68HC58FN
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC28
封裝： PLASTIC, LCC-28
文件頁數(shù)： 56/102頁
文件大小： 700K
代理商： MC68HC58FN
MC68HC58
DATA LINK CONTROLLER OPERATION
MOTOROLA
TECHNICAL DATA
4-13
Frames are sent in two basic modes:
A complete frame is loaded into the TxFIFO buffer for transmission (Normal
mode).
Bytes of the frame are continuously loaded into the TxFIFO buffer as the message
is being transmitted, until the entire frame has been sent (Block mode).
The DLC determines that a frame is completely loaded into the TxFIFO by reading a
“l(fā)oad as last byte of transmit data” command byte. If no such command byte has been
received, the transmitter operates in block mode until the command is received. The
host MCU can monitor transmitter activity by polling individual status bytes, or servic-
ing can be interrupt driven. Refer to 4.5 Block Mode Operation for more information.
The transmitter waits until either an entire frame is in the TxFIFO buffer, or until the
TxFIFO buffer is full before beginning a transmission. This prevents a data underrun
during transmission of the first frame byte. Once the J1850 bus is determined to be
idle, transmission and J1850 bus arbitration begin.
When a complete frame is in the TxFIFO buffer, the DLC status byte will indicate that
the TxFIFO buffer is full until the transmission is successfully completed.
A DLC automatically attempts to retransmit a frame if it loses arbitration or if errors are
detected during transmission. The completion code placed in the RxFIFO indicates to
the host MCU when a frame has lost arbitration.
The host MCU can terminate this automatic retry by writing a “terminate automatic re-
try ” (TAR) command byte to the DLC. When the DLC receives the TAR command, it
completes any current transmission, then clears the TxFIFO buffer. If no transmission
is in progress, and the TxFIFO buffer is full, the DLC attempts to transmit the frame in
the TxFIFO buffer once, then clears the TxFIFO buffer.
Since a frame remains in the TxFIFO buffer until it is successfully transmitted, a host
must clear the TxFIFO buffer if another frame is to be substituted for it. There are
several commands that can accomplish this. Refer to SECTION 5 CONTROL AND
STATUS CODES for more information. One of these commands and the command to
load the first byte of a new frame can be combined into a single byte that accompanies
the first byte of new data.
When a TxFIFO underrun occurs, the CRC is intentionally corrupted by being comple-
mented and appended to the transmission.
Figures 4-9 and 4-10 outline the basic software requirements for transferring data to
the DLC in serial mode for transmission onto the J1850 multiplex bus.
NOTE
Particular applications may require more extensive error monitoring
and handling routines than this flowchart displays. Conditions reflect-
ed in the retrieved status byte (received data bytes or J1850 bus sta-
tus) are also not addressed.
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