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參數(shù)資料
| 型號： | MC68HC58FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 53/102頁 |
| 文件大?。?/td> | 700K |
| 代理商： | MC68HC58FN |
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MOTOROLA
DATA LINK CONTROLLER OPERATION
MC68HC58
4-10
TECHNICAL DATA
Figure 4-6 SPI Transfer — Clock Polarity Low
Figure 4-7 SPI Transfer — Clock Polarity High
4.2.2.4 Initialization
Before the DLC is used for transmission or reception, it must be initialized. Initialization
is performed by loading a configuration data byte into the configuration byte register
with the “l(fā)oad as configuration byte—immediate” command. Once the configuration
byte is loaded following a reset of the DLC, the host can load message bytes to be
transmitted onto the J1850 bus into the DLC. Transmission will not begin until the DLC
determines that an idle bus condition exists on the J1850 bus. Figure 4-8 illustrates a
basic host/DLC initialization routine.
NOTE
Use the “l(fā)oad as configuration byte—immediate” command byte bit
combination only after a reset, for test purposes, or for changing the
interrupt mode or mask during normal operation. In the absence of
these conditions, use the “l(fā)oad as configuration byte” command.
CS
SOMI
SCLK
SIMO
S7
S6
S5
S4
S3
S2
S1
S0
R7
R6
R5
R4
R3
R2
R1
R0
X7
X6
X5
X4
X3
X2
X1
X0
C7
C6
C5
C4
C3
C2
C1
C0
COMMAND BYTE LATCHED
IN AT THIS POINT, AND ITS
CONTENTS WILL BE ACTED
ON WITHIN 2
S
DATA VALID IN THIS TIME PERIOD
NOTE: SCLK NORMALLY LOW (POLARITY = 0), PHASE = 0
DLC SPI TRANSFER 1
CS
SOMI
SCLK
SIMO
S7
S6
S5
S4
S3
S2
S1
S0
R7
R6
R5
R4
R3
R2
R1
R0
X7
X6
X5
X4
X3
X2
X1
X0
C7
C6
C5
C4
C3
C2
C1
C0
COMMAND BYTE LATCHED
IN AT THIS POINT, AND ITS
CONTENTS WILL BE ACTED
ON WITHIN 2
S
DATA VALID IN THIS TIME PERIOD
NOTE: SCLK NORMALLY HIGH (POLARITY = 1), PHASE = 1
DLC SPI TRANSFER 2
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