i.MX27 Data Sheet, Advance Information, Rev. 0.1
12
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Functional Description and Application Information
2.3.7
Clock and Reset Module (CRM)
The Clock and Reset Module (CRM) generates clock and reset signals used throughout the i.MX27
processor and for external peripherals. It also enables system software to control, customize, or read the
status of the following functions:
Chip ID
Multiplexing of I/O signals
I/O Driving Strength
I/O Pull Enable Control
Well-Bias Control
System boot mode selection
DPTC Control
2.3.8
CMOS Sensor Interface (CSI)
The CMOS Sensor Interface (CSI) is a logic interface that enables the i.MX27 processor to connect
directly to external CMOS sensors and CCIR656 video source.
The capabilities of the CSI include the following:
Configurable interface logic to support popular CMOS sensors in the market
Support traditional sensor timing interface
Support CCIR656 video interface, progressive mode for smart sensor, interlace mode for PAL and
NTSC input
8-bit input port for YCC, YUV, Bayer, or RGB data
32
×
32 FIFO storing image data supporting Core data read and DMA data burst transfer to system
memory
Full control of 8-bit and 16-bit data to 32-bit FIFO packing
Direct interface to eMMA-lt Pre-Processing block (PrP)
Single interrupt source to interrupt controller from maskable sensor interrupt sources: Start of
Frame, End of Frame, Change of Field, FIFO full
Configurable master clock frequency output to sensor
Asynchronous input logic design. Sensor master clock can be driven by either the i.MX27
processor or by external clock source.
Statistic data generation for Auto Exposure (AE) and Auto White Balance (AWB) control of the
camera (for Bayer data only)
2.3.9
Configurable Serial Peripheral Interface (CSPI)
The Configurable Serial Peripheral Interface (CSPI) is used for fast data communication with fewer
software interrupts. There are three CSPI modules in the i.MX27 processor, which provide a full-duplex
synchronous serial interface, capable of interfacing to the SPI master and slave devices. CSPI1 and CSPI2
are master/slave configurable and include three chip selects to support multiple peripherals. CSPI3 is only