參數(shù)資料
型號: MCIMX27
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Multimedia Applications Processor(多媒體應用處理器)
中文描述: 多媒體應用處理器(多媒體應用處理器)
文件頁數(shù): 58/118頁
文件大?。?/td> 1159K
代理商: MCIMX27
i.MX27 Data Sheet, Advance Information, Rev. 0.1
58
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Signal Descriptions
Figure 18. MII Transmit Signal Timing Diagram
3.5.8.3
MII Asynchronous Inputs Signal Timing (FEC_CRS and FEC_COL)
Figure 19
shows the MII asynchronous input timings, and
Table 26
lists the timing parameters.
Figure 19. MII Asynchronous Inputs Signal Timing Diagram
3.5.8.4
MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. The MDC frequency should
be equal to or less than 2.5 MHz to be compliant with IEEE 802.3 MII specification. However the FEC
can function correctly with a maximum MDC frequency of 15 MHz.
Figure 20
shows the MII serial management channel timings, and
Table 27
lists the timing parameters.
Table 25. MII Transmit Signal Timing Parameters
ID
Parameter
1
1
FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.
Min
Max
Unit
M5
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
5
ns
M6
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
20
ns
M7
FEC_TX_CLK pulse width high
35%
65%
FEC_TX_CLK period
M8
FEC_TX_CLK pulse width low
35%
65%
FEC_TX_CLK period
Table 26. MII Asynchronous Inputs Signal Timing Parameter
ID
Parameter
Min
Max
Unit
M9
1
1
FEC_COL has the same timing in 10 Mbit 7-wire interface mode.
FEC_CRS to FEC_COL minimum pulse width
1.5
FEC_TX_CLK period
FEC_TX_CLK (input)
FEC_TXD[3:0] (outputs)
FEC_TX_EN
FEC_TX_ER
M7
M8
M5
M6
FEC_CRS, FEC_COL
M9
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