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參數(shù)資料
| 型號： | MCIMX27 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Multimedia Applications Processor(多媒體應(yīng)用處理器) |
| 中文描述： | 多媒體應(yīng)用處理器（多媒體應(yīng)用處理器） |
| 文件頁數(shù)： | 55/118頁 |
| 文件大?。?/td> | 1159K |
| 代理商： | MCIMX27 |
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Signal Descriptions
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
55
3.5.7
Direct Memory Access Controller (DMAC)
After assertion of External DMA Request the DMA burst will start when the corresponding DMA channel
becomes the current highest priority channel. The External DMA Request should be kept asserted until it
is serviced by the DMAC. One External request will initiate at least one DMA burst.
The output External Grant signal from the DMAC is an active-low signal. This signal will be asserted
during the time when a DMA burst is ongoing for an External DMA Request, when the following
conditions are true:
The DMA channel for which the DMA burst is ongoing has requested source as external DMA
Request (as per RSSR settings).
REN and CEN bit of this channel are set.
External DMA Request is asserted.
Once the grant is asserted the External DMA Request will not be sampled until completion of the DMA
burst. The priority of the external request will become low, for the next consecutive burst, if another DMA
request signal is asserted.
The waveforms are shown for the worst case—that is, smallest burst (1 byte read/write). Minimum and
maximum timings for the External request and External grant signal are present in the data sheet.
Figure 15
shows the minimum time for which the External Grant signal remains asserted if External DMA
request is de-asserted immediately after sensing grant signal active.
Table 22. CSPI Interface Timing Parameters
Num
Characteristic
3.3 V
Unit
1
CSPI1_RDY to SSn output low
—
—
ns
2
SSn output low to first SCLK edge
2T
—
ns
3
Last SCLK edge to SSn output high
2T
—
ns
4
SSn output high to CSPI1_RDY low
0
—
ns
5
SSn output width
2T + WAIT
—
ns
6
SSn input low to first SCLK edge
—
—
ns
7
SSn input pulse width
0
—
ns
8
pause between data word
0
—
ns
Note:
T
= CSPI clock period
Note:
WAIT = Number of bit clocks or 32.768 kHz clocks as per the Sample Period Control Register value.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCIMX27_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processor |
| MCIMX27ADSE | 功能描述:開發(fā)板和工具包 - ARM I.MX27 ADS RoHS:否 制造商:Arduino 產(chǎn)品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
| MCIMX27ADSE | 制造商:Freescale Semiconductor 功能描述:Development Kit |
| MCIMX27EC | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processor |
| MCIMX27IPCAM | 功能描述:視頻 IC 開發(fā)工具 I.MX27 IP CAMERA REF RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Boards 類型:YPbPr to RGBHV Converters 工具用于評估:LMH1251 工作電源電壓:5 V |
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