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參數資料
| 型號： | MCIMX27 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Multimedia Applications Processor(多媒體應用處理器) |
| 中文描述： | 多媒體應用處理器（多媒體應用處理器） |
| 文件頁數： | 13/118頁 |
| 文件大小： | 1159K |
| 代理商： | MCIMX27 |
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Functional Description and Application Information
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
13
a master and has one chip-select signal. The transfer continuation function of the CSPI enables unlimited
length data transfers using 32-bit wide by 8-entry FIFO for both TX and RX data DMA support.
The CSPI Ready (SPI_RDY) and Chip Select (SS) control signals enable fast data communication with
fewer software interrupts. When the CSPI module is configured as a master, it uses a serial link to transfer
data between the CSPI and an external device. A chip-enable signal and a clock signal are used to transfer
data between these two devices. When the CSPI module is configured as a slave, the user can configure
the CSPI Control register to match the external SPI master’s timing.
2.3.10
Direct Memory Access Controller (DMAC)
The Direct Memory Access Controller (DMAC) provides 16 channels to support linear memory, 2D
memory, FIFO, and end-of-burst enable FIFO transfers to support a wide variety of DMA operations.
Features include the following:
Support of 16 channels linear memory, 2D memory, and FIFO for both source and destination
Support of 8-bit, 16-bit, or 32-bit FIFO port size and memory port size data transfer
Configurability of DMA burst length of up to a maximum of 16 words, 32 half-words, or 64 bytes
for each channel
Bus utilization control for a channel that is not triggered by DMA request
Interrupts that are provided to interrupt handler on bulk data transfer complete or transfer error
DMA burst time-out error to terminate DMA cycle when the burst cannot be completed in a
programmed timing period
Dedicated external DMA request and grant signal
Support of increment, decrement, and no increment for source and destination addressing
Support of DMA chaining
2.3.11
enhancedMultiMedia Accelerator Light (eMMA_lt)
The
enhanced
MultiMedia Accelerator Light (eMMA_lt) consists of the video pre-processor (PrP) and
post-processor (PP). In contrast with i.MX21 processor’s components, this eMMA does not include the
video codec. A more powerful video codec is included as a separate module.
Each module has individual control and configuration registers that are accessed via the IP interface, and
are capable of bus mastering the AMBA bus to independently access system memory without any CPU
intervention. This enables each module to be used independently of each other, and enables the
pre-processor and post-processor modules to provide acceleration features for other software codec
implementations and image processing software. These blocks work together to provide video
acceleration, and to off-load the CPU from computation intensive tasks. The PrP and PP can be used for
generic video pre- and post-processing, such as scaling, resizing, and color space conversions. A
32-bit-to-64-bit AHB gasket is used to convert a PrP AHB bus from a 32-bit to 64-bit protocol. A bypass
function is implemented to bypass this 64-bit gasket if it is not needed.
eMMA_lt supports the following image/video processing features:
Pre-processor:
— Data input:
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MCIMX27_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processor |
| MCIMX27ADSE | 功能描述:開發(fā)板和工具包 - ARM I.MX27 ADS RoHS:否 制造商:Arduino 產品:Development Boards 工具用于評估:ATSAM3X8EA-AU 核心:ARM Cortex M3 接口類型:DAC, ICSP, JTAG, UART, USB 工作電源電壓:3.3 V |
| MCIMX27ADSE | 制造商:Freescale Semiconductor 功能描述:Development Kit |
| MCIMX27EC | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processor |
| MCIMX27IPCAM | 功能描述:視頻 IC 開發(fā)工具 I.MX27 IP CAMERA REF RoHS:否 制造商:Texas Instruments 產品:Evaluation Boards 類型:YPbPr to RGBHV Converters 工具用于評估:LMH1251 工作電源電壓:5 V |
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