參數(shù)資料
型號(hào): MCIMX27
廠(chǎng)商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Multimedia Applications Processor(多媒體應(yīng)用處理器)
中文描述: 多媒體應(yīng)用處理器(多媒體應(yīng)用處理器)
文件頁(yè)數(shù): 50/118頁(yè)
文件大?。?/td> 1159K
代理商: MCIMX27
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i.MX27 Data Sheet, Advance Information, Rev. 0.1
50
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Signal Descriptions
3.5.3.1
General Timing Requirements
These are the general timing requirements for the ATA interface signals.
NOTE:
SRISE and SFALL meets this requirement when measured at the sender’s connector from 10–90% of full signal
amplitude with all capacitive loads from 15 pf through 40 pf where all signals have the same capacitive load value.
Figure 8. ATA interface Signals Timing Diagram
3.5.4
Digital Audio Mux (AUDMUX)
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSI, SAP) and external serial interfaces (audio and voice codecs). The AC timing
of AUDMUX external pins is hence governed by SSI and SAP modules. Please refer to their respective
electrical specifications.
3.5.5
CMOS Sensor Interface (CSI)
This section describes the electrical information (AC timing) of the CSI.
3.5.5.1
Gated Clock Mode Timing
VSYNC, HSYNC, and PIXCLK signals are used in this mode. A frame starts with a rising/falling edge on
VSYNC, then HSYNC goes high and holds for the entire line. The pixel clock is valid as long as HSYNC
is high.
Figure 9
and
Figure 10
depict the gated clock mode timings of CSI, and
Table 20
lists the timing
parameters.
Table 19. AC Characteristics of All Interface Signals
ID
Parameter
Symbol
Min
Max
Unit
SI1
Rising edge slew rate for any signal on ATA
interface (see note)
S
rise
1.25
V/ns
SI2
Falling edge slew rate for any signal on ATA
interface (see note)
S
fall
1.25
V/ns
SI3
Host interface signal capacitance at the host
connector
C
host
20
pF
ATA Interface Signals
SI1
SI2
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