Functional Description and Application Information
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
7
LCDC
Liquid Crystal
Display
Controller
Multimedia
Interface
The LCDC provides display data for external gray-scale or
color LCD panels.
2.3.20/18
M3IF
Multi-Master
Memory
Interface
External
Memory
Interface
The M3IF controls memory accesses from one or more
masters through different port interfaces to different external
memory controllers ESDCTL/MDDRC, PCMCIA, NFC, and
WEIM.
2.3.21/18
MAX
Multi-layer AHB
Crossbar
Switch
Bus Control
The ARM926EJ-S processor’s instruction and data buses and
all alternate bus master interfaces arbitrate for resources via a
6
×
3 MAX. There are six fully functional master ports (M0–M5)
and three fully functional slave ports (S0–S2). The MAX is
uni-directional. All master and slave ports are AHB-Lite
compliant.
2.3.22/18
MSHC
Memory Stick
Host Controller
Connectivity
Peripheral
The MSHC is placed in between the AIPI and the customer
memory stick to support data transfer from the i.MX27 device
to the customer memory stick.
2.3.23/19
NFC
NAND Flash
Controller
External
Memory
Interface
The NFC is a submodule of EMI. The NFC implements the
interface to standard NAND Flash memory devices.
2.3.24/19
PCMCIA
Personal
Computer
Memory Card
International
Association
External
Memory
Interface
The PCMCIA host adapter module provides the control logic
for PCMCIA socket interfaces, and requires some additional
external analog power switching logic and buffering.
2.3.25/20
PLL
Phase Lock
Loop
Clock and
Reset Control
The two DPLLs provide clock generation in digital and mixed
analog/digital chips designed for wireless communication and
other applications.
2.3.26/20
PWM
Pulse-Width
Modulator
Timer
Peripheral
The PWM has a 16-bit counter and is optimized to generate
sound from stored sample audio images. It can also generate
tones.
2.3.27/20
RTC
Real Time
Clock
Timer
Peripheral
The RTC module provides a current stamp of seconds,
minutes, hours, and days. Alarm and timer functions are also
available for programming. The RTC supports dates from the
year 1980 to 2050.
2.3.28/20
RTIC
Run-Time
Integrity
Checkers
Security
The RTIC ensures the integrity of the contents of the peripheral
memory and assists with boot authentication.
2.3.29/21
SAHARA2
Symmetric/
Asymmetric
Hashing and
Random
Accelerator
Security
SAHARA2 is a security co-processor which forms part of the
Platform Independent Security Architecture (PISA), and can be
used on cell phone baseband processors or wireless PDAs.
2.3.30/21
Table 2. Digital and Analog Modules (continued)
Block Mnemonic
Block Name
Functional
Grouping
Brief Description
Section/
Page