參數(shù)資料
型號: MCIMX537CVV8C
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封裝: 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件頁數(shù): 100/172頁
文件大?。?/td> 4562K
代理商: MCIMX537CVV8C
Electrical Characteristics
i.MX53 Applications Processors for Industrial Products, Rev. 3
Freescale Semiconductor
33
4.3.5
LVDS I/O DC Parameters
The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
Table 16 shows the Low Voltage Differential Signaling (LVDS) DC electrical characteristics.
4.4
Output Buffer Impedance Characteristics
This section defines the I/O Impedance parameters of the i.MX53 processor for the following I/O types:
General Purpose I/O (GPIO)
Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2, and DDR3 modes
Ultra High Voltage I/O (UHVIO)
LVDS I/O
NOTE
Output driver impedance is measured with “l(fā)ong” transmission line of
impedance Ztl attached to I/O pad and incident wave launched into
transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines
specific voltage of incident wave relative to OVDD. Output driver
impedance is calculated from this voltage divider (see Figure 4).
1 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must
be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
2
To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current
DC level to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply
when hysteresis is enabled.
3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
4 Use an off-chip pull resistor of less than 60 k
Ω to override this keeper.
Table 16. LVDS DC Electrical Characteristics
DC Electrical Characteristics
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Differential Voltage
VOD
Rload=100
Ω
padP, –padN
250
350
450
mV
Output High Voltage
VOH
1.25
1.375
1.6
V
Output Low Voltage
VOL
0.9
1.025
1.25
Offset Voltage
VOS
1.125
1.2
1.375
相關(guān)PDF資料
PDF描述
MCM16Y1BACFT16 16-BIT, MROM, MICROCONTROLLER, PQFP160
MCM16Y1BGCFT16 16-BIT, MROM, MICROCONTROLLER, PQFP160
M68HC16Y1CFC 16-BIT, MROM, MICROCONTROLLER, PQFP16
MCV14AI/SL 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14
MCV14ATI/SL 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MCIMX537CVV8C 制造商:Freescale Semiconductor 功能描述:IC 32-BIT MPU 800 MHZ 529-BGA
MCIMX537CVV8CR2 功能描述:處理器 - 專門應(yīng)用 iMX53 Rev 2.1 Indust RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX538DZK1C 功能描述:處理器 - 專門應(yīng)用 I.MX53 2.1 POP RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432
MCIMX53EVK 制造商:Freescale Semiconductor 功能描述:
MCIMX53-LVDS 制造商:Freescale Semiconductor 功能描述:I.MX53 XGA DISPLAY LVDS DEV BOARD 制造商:Freescale Semiconductor 功能描述:I.MX53, XGA DISPLAY, LVDS, DEV BOARD 制造商:Freescale Semiconductor 功能描述:I.MX53, XGA DISPLAY, LVDS CONNECTOR, DEV BOARD; Silicon Manufacturer:Freescale; Core Architecture:ARM; Core Sub-Architecture:Cortex-A8; Silicon Core Number:i.MX5; Silicon Family Name:i.MX53