參數(shù)資料
型號: MCIMX537CVV8C
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封裝: 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件頁數(shù): 19/172頁
文件大?。?/td> 4562K
代理商: MCIMX537CVV8C
Electrical Characteristics
i.MX53 Applications Processors for Industrial Products, Rev. 3
Freescale Semiconductor
115
4.7.12.3
UDMA Output Timing
Figure 71 shows timing when the UDMA out transfer starts, Figure 72 shows timing when the UDMA out
host terminates transfer, Figure 73 shows timing when the UDMA out device terminates transfer, and
Table 75 lists the timing parameters for UDMA out burst.
Figure 71. UDMA Out Transfer Starts Timing Diagram
tcyc
tc1
(tcyc – tskew) > T
T big enough
trp
trp (min) = time_rp
× T – (tskew1 + tskew2 + tskew6)
time_rp
—tx11
(time_rp
× T) – (tco + tsu + 3T + 2 ×tbuf + 2×tcable2) > trfs (drive)
time_rp
tmli
tmli1
tmli1 (min) = (time_mlix + 0.4)
× T
time_mlix
tzah
tzah (min) = (time_zah + 0.4)
× T
time_zah
tdzfs
tdzfs = (time_dzfs
× T) – (tskew1 + tskew2)
time_dzfs
tcvh
tcvh = (time_cvh
×T) – (tskew1 + tskew2)
time_cvh
—ton
toff2
ton = time_on
× T – tskew1
toff = time_off
× T – tskew1
1 There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last
active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
2 Make ton and toff big enough to avoid bus contention.
Table 74. UDMA in Burst Timing Parameters (continued)
ATA
Parameter
from
Figure 68,
Figure 69,
Figure 70
Description
Controlling Variable
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