參數(shù)資料
型號: MCIMX537CVV8C
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封裝: 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件頁數(shù): 74/172頁
文件大?。?/td> 4562K
代理商: MCIMX537CVV8C
Package Information and Contact Assignments
i.MX53 Applications Processors for Industrial Products, Rev. 3
Freescale Semiconductor
165
SD1_CLK
E16
NVCC_SD1
UHVIO
ALT1
GPIO-1
gpio1_GPIO[20]
Input
100 K
Ω PU
SD1_CMD
F18
NVCC_SD1
UHVIO
ALT1
GPIO-1
gpio1_GPIO[18]
Input
100 K
Ω PU
SD1_DATA0
A20
NVCC_SD1
UHVIO
ALT1
GPIO-1
gpio1_GPIO[16]
Input
100 K
Ω PU
SD1_DATA1
C17
NVCC_SD1
UHVIO
ALT1
GPIO-1
gpio1_GPIO[17]
Input
100 K
Ω PU
SD1_DATA2
F17
NVCC_SD1
UHVIO
ALT1
GPIO-1
gpio1_GPIO[19]
Input
100 K
Ω PU
SD1_DATA3
F16
NVCC_SD1
UHVIO
ALT1
GPIO-1
gpio1_GPIO[21]
Input
100 K
Ω PU
SD2_CLK
E14
NVCC_SD2
UHVIO
ALT1
GPIO-1
gpio1_GPIO[10]
Input
100 K
Ω PU
SD2_CMD
C15
NVCC_SD2
UHVIO
ALT1
GPIO-1
gpio1_GPIO[11]
Input
100 K
Ω PU
SD2_DATA0
D13
NVCC_SD2
UHVIO
ALT1
GPIO-1
gpio1_GPIO[15]
Input
100 K
Ω PU
SD2_DATA1
C14
NVCC_SD2
UHVIO
ALT1
GPIO-1
gpio1_GPIO[14]
Input
100 K
Ω PU
SD2_DATA2
D14
NVCC_SD2
UHVIO
ALT1
GPIO-1
gpio1_GPIO[13]
Input
100 K
Ω PU
SD2_DATA3
E13
NVCC_SD2
UHVIO
ALT1
GPIO-1
gpio1_GPIO[12]
Input
100 K
Ω PU
TEST_MODE
D17
NVCC_RESET
LVIO
ALT0
tcu_TEST_MOD
E
Input
100 K
Ω PD
TVCDC_IOB_
BACK
AB19
TVDAC_AHVDDRG
B
ANALOG
TVE
TVCDC_IOB_BA
CK
——
TVCDC_IOG_
BACK
AC20
TVDAC_AHVDDRG
B
ANALOG
TVE
TVCDC_IOG_BA
CK
——
TVCDC_IOR_
BACK
AB21
TVDAC_AHVDDRG
B
ANALOG
TVE
TVCDC_IOR_BA
CK
——
TVDAC_COM
P
AA19
TVDAC_AHVDDRG
B
ANALOG
TVE
TVDAC_COMP
TVDAC_IOB
AC19
TVDAC_AHVDDRG
B
ANALOG
TVE
TVDAC_IOB
TVDAC_IOG
AB20
TVDAC_AHVDDRG
B
ANALOG
TVE
TVDAC_IOG
TVDAC_IOR
AC21
TVDAC_AHVDDRG
B
ANALOG
TVE
TVDAC_IOR
TVDAC_VREF Y18
TVDAC_AHVDDRG
B
ANALOG
TVE
TVDAC_VREF
USB_H1_DN
B17
USB_H1_VDDA25,
USB_H1_VDDA33
ANALOG50 —
USB
USB_H1_DN
Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Contact Name
Package
Contact
Assign
ment
Power Rail
I/O Buffer
Type
Out of Reset Condition1
Alt.
Mode
B
loc
k
Insta
n
ce
Block I/O
Direction
Config./
Value
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