參數(shù)資料
型號: MCIMX537CVV8C
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封裝: 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件頁數(shù): 49/172頁
文件大小: 4562K
代理商: MCIMX537CVV8C
i.MX53 Applications Processors for Industrial Products, Rev. 3
142
Freescale Semiconductor
Electrical Characteristics
4.7.18.2
Parallel Interface (Normal ULPI) Timing
Electrical and timing specifications of Parallel Interface (Normal ULPI) for Host Port2 and Port3 are
presented in the subsequent sections.
Figure 97. USB Transmit/Receive Waveform in Parallel Mode
4.7.19
USB PHY Parameters
This section describes the USB-OTG PHY and the USB Host port PHY parameters.
4.7.19.1
USB PHY AC Parameters
Table 101 lists the AC timing parameters for USB PHY.
Table 99. Signal Definitions - Parallel Interface (Normal ULPI)
Name
Direction
Signal Description
USB_Clk
In
Interface clock. All interface signals are synchronous to Clock.
USB_Data[7:0]
I/O
Bi-directional data bus, driven low by the link during idle. Bus
ownership is determined by Dir.
USB_Dir
In
Direction. Control the direction of the Data bus.
USB_Stp
Out
Stop. The link asserts this signal for 1 clock cycle to stop the
data stream currently on the bus.
USB_Nxt
In
Next. The PHY asserts this signal to throttle the data.
Table 100. USB Timing Specification for Normal ULPI Mode
ID
Parameter
Min
Max
Unit
Conditions /
Reference Signal
US15
Setup Time (Dir&Nxt in, Data in)
6.0
ns
10 pF
US16
Hold Time (Dir&Nxt in, Data in)
0.0
ns
10 pF
US17
Output Delay Time (Stp out, Data out
9.0
ns
10 pF
USB_Stp
USB_Dir/Nxt
US17
US16
USB_Data
US15
US16
US15
US17
USB_Clk
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