參數(shù)資料
型號： MCIMX537CVV8C
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封裝： 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件頁數(shù)： 114/172頁
文件大?。?/td> 4562K
代理商： MCIMX537CVV8C
i.MX53 Applications Processors for Industrial Products, Rev. 3
46
Freescale Semiconductor
Electrical Characteristics
4.6.5
NAND Flash Controller (NFC) Parameters
This section provides the relative timing requirements among various signals of NFC at the module level,
in each operational mode.
Timing parameters in Figure 10, Figure 11, Figure 12, Figure 13, Figure 15, and Table 35 show the default
NFC mode (asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B.
Timing parameters in Figure 10, Figure 11, Figure 12, Figure 14, Figure 15, and Table 35 show symmetric
NFC mode using one Flash clock cycle per one access of RE_B and WE_B.
With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20%
of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is
20 pF (except for NF16 - 40 pF) and there is maximum drive strength on all contacts.
All timing parameters are a function of T, which is the period of the flash_clk clock (“enfc_clk” at system
level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The
clock is derived from emi_slow_clk after single divider.
Figure 34 demonstrates several examples of clock frequency settings.
NOTE
A potential limitation for minimum clock frequency may exist for some
devices. When the clock frequency is too low, the data bus capturing might
occur after the specified trhoh (RE_B high to output hold) period. Setting the
clock frequency above 25.6 MHz (that is, T = 39 ns) guaranties a proper
operation for devices having trhoh > 15 ns. It is also recommended that the
NFC_FREQ_SEL Fuse be set accordingly to initiate the boot with
33.33 MHz clock.
4 T
dpdref is the time period of the reference clock after predivider. According to the specification, the maximum lock time in FOL
mode is 398 cycles of divided reference clock when DPLL starts after full reset.
5 Tdck is the time period of the output clock, dpdck_2.
Table 34. NFC Clock Settings Examples
emi_slow_clk (MHz)
nfc_podf (Division Factor)
enfc_clk (MHz)
T-Clock Period (ns)
100 (Boot mode)
71
1 Boot value NFC_FREQ_SEL Fuse High (burned)
14.29
70
32
2 Boot value NFC_FREQ_SEL Fuse Low
33.33
30
133
4
33.33
30
3
44.333
3 For RBB_MODE=1, using NANDF_RB0 signal for ready/busy indication. This mode require setting the delay line. See the
Reference Manual for details.
22.5
2663
15
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相關代理商/技術參數(shù)
參數(shù)描述
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