參數(shù)資料
型號: MCIMX537CVV8C
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 800 MHz, RISC PROCESSOR, PBGA529
封裝: 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, TEPBGA-529
文件頁數(shù): 27/172頁
文件大?。?/td> 4562K
代理商: MCIMX537CVV8C
i.MX53 Applications Processors for Industrial Products, Rev. 3
122
Freescale Semiconductor
Electrical Characteristics
4.7.15
SPDIF Timing Parameters
The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When
encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.
Table 80 and Figures , show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format
(SPDIF), including the timing of the modulating Rx clock (SRCK) for SPDIF in Rx mode and the timing
of the modulating Tx clock (STCLK) for SPDIF in Tx mode.
SJ9
TMS, TDI data hold time
25
ns
SJ10
TCK low to TDO data valid
44
ns
SJ11
TCK low to TDO high impedance
44
ns
SJ12
TRST assert time
100
ns
SJ13
TRST set-up time to TCK low
40
ns
1 T
DC = target frequency of SJC
2 V
M = mid-point voltage
Table 80. SPDIF Timing Parameters
Characteristics
Symbol
Timing Parameter Range
Units
Min
Max
SPDIFIN Skew: asynchronous inputs, no specs apply
0.7
ns
SPDIFOUT output (Load = 50pf)
Skew
Transition rising
Transition falling
1.5
24.2
31.3
ns
SPDIFOUT1 output (Load = 30pf)
Skew
Transition rising
Transition falling
1.5
13.6
18.0
ns
Modulating Rx clock (SRCK) period
srckp
40.0
ns
SRCK high period
srckph
16.0
ns
SRCK low period
srckpl
16.0
ns
Modulating Tx clock (STCLK) period
stclkp
40.0
ns
STCLK high period
stclkph
16.0
ns
STCLK low period
stclkpl
16.0
ns
Table 79. JTAG Timing (continued)
ID
Parameter1,2
All Frequencies
Unit
Min
Max
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