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參數(shù)資料
| 型號： | MPC5200 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Hardware Specifications |
| 中文描述： | 硬件規(guī)格 |
| 文件頁數(shù)： | 37/80頁 |
| 文件大小： | 790K |
| 代理商： | MPC5200 |
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Electrical and Thermal Characteristics
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
37
(t)
LI
0
150
0
150
0
150
Limited Interlock time.
1,2
A8.34
(t)
MLI
20
—
20
—
20
—
Interlock time with minimum.
1,2
A8.35
(t)
UI
0
—
0
—
0
—
Unlimited interlock time.
1,2
A8.36
(t)
AZ
—
10
—
10
—
10
Maximum time allowed for output drivers to release
from being asserted or negated
A8.37
(t)
ZAH
20
—
20
—
20
—
Minimum delay time required for output drivers to
assert or negate from released state
A8.38
(t)
ZAD
0
—
0
—
0
—
A8.39
(t)
ENV
20
70
20
70
20
70
Envelope time—from DMACK to STOP and
HDMARDY during data out burst initiation.
A8.40
(t)
SR
—
50
—
30
—
20
STROBE to DMARDY time, if DMARDY is negated
before this long after STROBE edge, the recipient
receives no more than one additional data word.
A8.41
(t)
RFS
—
75
—
60
—
50
Ready-to-Final STROBE time—no STROBE edges
are sent this long after negation of DMARDY.
A8.42
(t)
RP
160
—
125
—
100
—
Ready-to-Pause time—the time recipient waits to
initiate pause after negating DMARDY.
A8.43
(t)
IORDYZ
—
20
—
20
—
20
Pull-up time before allowing IORDY to be released.
A8.44
(t)
ZIORDY
0
—
0
—
0
—
Minimum time drive waits before driving IORDY
A8.45
(t)
ACK
20
—
20
—
20
—
Setup and hold times for DMACK, before assertion or
negation.
A8.46
(t)
SS
50
—
50
—
50
—
Time from STROBE edge to negation of DMARQ or
assertion of STOP, when sender terminates a burst.
A8.47
NOTES:
1
t
UI
, t
MLI
, t
LI
indicate sender-to-recipient or recipient-to-sender interlocks. That is, one agent (either sender or recipient)
is waiting for the other agent to respond with a signal before proceeding.
t
UI
is an unlimited interlock that has no maximum time value.
t
MLI
is a limited time-out that has a defined minimum.
t
LI
is a limited time-out that has a defined maximum.
2
All timing parameters are measured at the connector of the drive to which the parameter applies. For example, the
sender shall stop generating STROBE edges t
RFS
after negation of DMARDY. Both STROBE and DMARDY timing
measurements are taken at the connector of the sender. Even though the sender stops generating STROBE edges,
the receiver may receive additional STROBE edges due to propagation delays. All timing measurement switching
points (low to high and high to low) are taken at 1
.
5 V.
Table 29. Ultra DMA Timing Specification (continued)
Name
MODE 0
(ns)
MODE 1
(ns)
MODE 2
(ns)
Comment
SpecID
Min
Max
Min
Max
Min
Max
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC5200B | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM/DDR Memory Controller |
| MPC5200B_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM / DDR Memory Controller |
| MPC5200B_10 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM/DDR Memory Controller |
| MPC5200BDS | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Technical Data |
| MPC5200BV400 | 功能描述:微處理器 - MPU 400MHz 760MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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