參數(shù)資料
型號: MPC5200
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Hardware Specifications
中文描述: 硬件規(guī)格
文件頁數(shù): 62/80頁
文件大?。?/td> 790K
代理商: MPC5200
MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor
62
3.3.17 IEEE 1149.1 (JTAG) AC Specifications
Figure 47. Timing Diagram—JTAG Clock Input
Table 51. JTAG Timing Specification
Sym
Characteristic
Min
Max
Unit
SpecID
TCK frequency of operation.
0
25
MHz
A17.1
1
TCK cycle time.
40
ns
A17.2
2
TCK clock pulse width measured at 1.5V.
1
.
08
ns
A17.3
3
TCK rise and fall times.
TRST setup time to tck falling edge
1
.
0
3
ns
A17.4
4
NOTES:
1
TRST is an asynchronous signal. The setup time is for test purposes only.
2
Non-test, other than TDI and TMS, signal input timing with respect to TCK.
3
Non-test, other than TDO, signal output timing with respect to TCK.
10
ns
A17.5
5
TRST assert time.
Input data setup time
2
.
Input data hold time
2
.
TCK to output data valid
3
.
TCK to output high impedance
3
.
5
ns
A17.6
6
5
ns
A17.7
7
15
ns
A17.8
8
0
30
ns
A17.9
9
0
30
ns
A17.10
10
TMS, TDI data setup time.
5
ns
A17.11
11
TMS, TDI data hold time.
1
ns
A17.12
12
TCK to TDO data valid.
0
15
ns
A17.13
13
TCK to TDO high impedance.
0
15
ns
A17.14
TCK
VM
VM
VM
3
3
2
2
1
VM = Midpoint Voltage
Numbers shown reference
Table 51
.
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