參數(shù)資料
型號(hào): MPC5200
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: Hardware Specifications
中文描述: 硬件規(guī)格
文件頁(yè)數(shù): 60/80頁(yè)
文件大?。?/td> 790K
代理商: MPC5200
MPC5200 Data Sheet, Rev. 4
Electrical and Thermal Characteristics
Freescale Semiconductor
60
NOTE
Output timing was specified at a nominal 50 pF load.
Figure 45. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)
Table 49. Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1)
Sym
Description
Min
Max
Units
SpecID
1
SCK cycle time, programable in the PSC CCS register
30.0
ns
A15.56
2
SCK pulse width, 50% SCK cycle time
15.0
ns
A15.57
3
Slave select clock delay
0.0
ns
A15.58
4
Output data valid
14.0
ns
A15.59
5
Input Data setup time
2.0
ns
A15.60
6
Input Data hold time
1.0
ns
A15.61
7
Slave disable lag time
0.0
ns
A15.62
8
Minimum Sequential Transfer delay = 2 * IP-Bus clock cycle time
30.0
ns
A15.63
SCK
(CLKPOL=0)
SCK
(CLKPOL=1)
MOSI
Input
Input
Input
SS
Input
MISO
Output
1
2
2
7
8
3
4
6
5
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