參數(shù)資料
型號: MPC5200
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Hardware Specifications
中文描述: 硬件規(guī)格
文件頁數(shù): 51/80頁
文件大?。?/td> 790K
代理商: MPC5200
Electrical and Thermal Characteristics
MPC5200 Data Sheet, Rev. 4
Freescale Semiconductor
51
Figure 36. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)
3.3.12 MSCAN
The CAN functions are available as RX and TX pins at normal IO pads (I
2
C1+GPTimer or PSC2). There
is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured.
3.3.13 I
2
C
Table 40. I
2
C Input Timing Specifications—SCL and SDA
Sym
Description
Min
Max
Units
SpecID
1
Start condition hold time
2
IP-Bus Cycle
1
NOTES:
1
Inter Peripheral Clock is defined in the MPC5200 User Manual [1].
A13.1
2
Clock low period
8
IP-Bus Cycle
1
A13.2
4
Data hold time
0.0
ns
A13.3
6
Clock high time
4
IP-Bus Cycle
1
A13.4
7
Data setup time
0.0
ns
A13.5
8
Start condition setup time (for repeated start condition
only)
2
IP-Bus Cycle
1
A13.6
9
Stop condition setup time
2
IP-Bus Cycle
1
A13.7
SCK
(CLKPOL=0)
SCK
(CLKPOL=1)
MOSI
Input
Input
Input
SS
Input
MISO
Output
1
2
2
7
8
3
4
6
5
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