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參數(shù)資料
| 型號(hào)： | MPC5200 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Hardware Specifications |
| 中文描述： | 硬件規(guī)格 |
| 文件頁數(shù)： | 74/80頁 |
| 文件大?。?/td> | 790K |
| 代理商： | MPC5200 |
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MPC5200 Data Sheet, Rev. 4
System Design Information
Freescale Semiconductor
74
5.3.2
Pull-up Requirements for the PCI Control Lines
If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as
indicated by the PCI Local Bus specification [4]. This is also required for MOST/Graphics and Large Flash
Mode.
PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to
ensure that they contain stable values when no agent is actively driving the bus. This includes
PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL, PCI_STOP, PCI_SERR, PCI_PERR, and
PCI_REQ.
5.3.3
Pull-up/Pull-down Requirements for MEM_MDQS pins
(SDRAM)
The MEM_MDQS[3:0] signals are not used with SDR memories and require pull-up or pull-down
resistors in SDRAM mode.
5.4
JTAG
The MPC5200 provides the user an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also
provides a Common On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The
COP Interface provides access to the MPC5200's imbedded Freescale (formerly Motorola) MPC603e
G2_LE processor. This interface provides a means for executing test routines and for performing software
development & debug functions.
5.4.1
JTAG_TRST
Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional
in the IEEE 1149.1 specification but is provided on all processors that implement the PowerPC
architecture. To obtain a reliable power-on reset performance, the JTAG_TRST signal must be asserted
during power-on reset.
5.4.1.1
The JTAG interface can control the direction of the MPC5200 I/O pads via the boundary scan chain. The
JTAG module must be reset before the MPC5200 comes out of power-on reset; do this by asserting
JTAG_TRST before PORRESET is released.
JTAG_TRST and PORRESET
For more details refer to the Reset and JTAG Timing Specification.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC5200B | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM/DDR Memory Controller |
| MPC5200B_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM / DDR Memory Controller |
| MPC5200B_10 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SDRAM/DDR Memory Controller |
| MPC5200BDS | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Technical Data |
| MPC5200BV400 | 功能描述:微處理器 - MPU 400MHz 760MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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