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參數(shù)資料
| 型號(hào)： | MPC7457EC |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 16/68頁 |
| 文件大小： | 1755K |
| 代理商： | MPC7457EC |
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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
16
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 3
provides the SYSCLK input timing diagram.
Figure 3. SYSCLK Input Timing Diagram
5.2.2
Processor Bus AC Specifications
Table 9
provides the processor bus AC timing specifications for the MPC7457 as defined in
Figure 4
and
Figure 5
.
Timing specifications for the L3 bus are provided in
Section 5.2.3, “L3 Clock AC Specifications
.”
SYSCLK cycle time
t
SYSCLK
6.0
30
6.0
30
6.0
30
6.0
30
ns
2
SYSCLK rise and fall time
t
KR
, t
KF
—
1.0
—
1.0
—
1.0
—
1.0
ns
3
SYSCLK duty cycle measured
at OV
DD
/2
t
KHKL
/
t
SYSCLK
40
60
40
60
40
60
40
60
%
4
SYSCLK cycle-to-cycle jitter
—
150
—
150
—
150
—
150
ps
5, 6
Internal PLL relock time
—
100
—
100
—
100
—
100
μ
s
7
Notes
:
1.
Caution
: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.9.1, “PLL Configuration,” for valid PLL_CFG[0:4]
settings.
Assumes lightly-loaded, single-processor system; see
Section 5.2.1, “Clock AC Specifications
” for more information.
Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V.
Timing is guaranteed by design and characterization.
Guaranteed by design.
The SYSCLK driver’s closed loop jitter bandwidth should be less than 1.5 MHz at –3 dB.
Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for
PLL lock after a stable V
DD
and SYSCLK are reached during the power-on reset sequence. This specification also applies
when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held
asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
2.
3.
4.
5.
6.
7.
Table 8. Clock AC Timing Specifications (continued)
At recommended operating conditions. See
Table 4
.
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
Notes
867 MHz
1000 MHz
1200 MHz
1267 MHz
Min
Max
Min
Max
Min
Max
Min
Max
SYSCLK
VM
VM
VM
CV
IH
CV
IL
VM = Midpoint Voltage (OV
DD
/2)
t
SYSCLK
t
KR
t
KF
t
KHKL
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