參數(shù)資料
型號(hào)： MPC7457EC
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： RISC Microprocessor Hardware Specifications
中文描述： RISC微處理器硬件規(guī)格
文件頁(yè)數(shù)： 47/68頁(yè)
文件大?。?/td> 1755K
代理商： MPC7457EC
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
47
System Design Information
9
System Design Information
This section provides system and thermal design recommendations for successful application of the MPC7457.
9.1
Clocks
The following sections provide more detailed information regarding the clocking of the MPC7457.
9.1.1
Core Clocks and PLL Configuration
The MPC7457 PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency, the PLL
configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the
MPC7457 is shown in
Table 18
for a set of example frequencies. In this example, shaded cells represent settings
that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the 1-GHz
column in
Table 8
. Note that these configurations were different in some earlier MPC7450-family devices and care
should be taken when upgrading to the MPC7457 to verify the correct PLL settings for an application.
Table 18. MPC7457 Microprocessor PLL Configuration Example for 1267 MHz Parts
PLL_CFG[0:4]
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus (SYSCLK) Frequency
33.3
MHz
50
MHz
66.6
MHz
75
MHz
83
MHz
100
MHz
133
MHz
167
MHz
01000
2x
2x
10000
3x
2x
10100
4x
2x
667
(1333)
10110
5x
2x
667
(1333)
835
(1670)
10010
5.5x
2x
733
(1466)
919
(1837)
11010
6x
2x
600
(1200)
800
(1600)
1002
(2004)
01010
6.5x
2x
650
(1300)
866
(1730)
1086
(2171)
00100
7x
2x
700
(1400)
931
(1862)
1169
(2338)
00010
7.5x
2x
623
(1245)
750
(1500)
1000
(2000)
1253
(2505)
11000
8x
2x
600
(1200)
664
(1328)
800
(1600)
1064
(2128)
01100
8.5x
2x
638
(1276)
706
(1412)
850
(1700)
1131
(2261)
01111
9x
2x
600
(1200)
675
(1350)
747
(1494)
900
(1800)
1197
(2394)
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