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參數(shù)資料
| 型號： | MPC7457EC |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 52/68頁 |
| 文件大?。?/td> | 1755K |
| 代理商： | MPC7457EC |
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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
52
Freescale Semiconductor
System Design Information
9.5
Output Buffer DC Impedance
The MPC7457 processor bus and L3 I/O drivers are characterized over process, voltage, and temperature. To
measure Z
0
, an external resistor is connected from the chip pad to OV
DD
or GND. Then, the value of each resistor
is varied until the pad voltage is OV
DD
/2 (see
Figure 23
).
The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When
data is held low, SW2 is closed (SW1 is open), and R
N
is trimmed until the voltage at the pad equals OV
DD
/2. R
N
then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and
R
P
is trimmed until the voltage at the pad equals OV
DD
/2. R
P
then becomes the resistance of the pull-up devices. R
P
and R
N
are designed to be close to each other in value. Then, Z
0
= (R
P
+ R
N
)/2.
Figure 25. Driver Impedance Measurement
Table 21
summarizes the signal impedance results. The impedance increases with junction temperature and is
relatively unaffected by bus voltage.
9.6
Pull-Up/Pull-Down Resistor Requirements
The MPC7457 requires high-resistive (weak: 4.7-k
) pull-up resistors on several control pins of the bus interface to
maintain the control signals in the negated state after they have been actively negated and released by the MPC7457
or other bus masters. These pins are: TS, ARTRY, SHDO, and SHD1.
Some pins designated as being for factory test must be pulled up to OV
DD
or down to GND to ensure proper device
operation. For the MPC7447, 360 BGA, the pins that must be pulled up to OV
DD
are: LSSD_MODE and TEST[0:3];
the pins that must be pulled down to GND are: L1_TSTCLK and TEST[4]. For the MPC7457, 483 BGA, the pins
that must be pulled up to OV
DD
are: LSSD_MODE and TEST[0:5]; the pins that must be pulled down are:
Table 21. Impedance Characteristics
V
DD
= 1.5 V, OV
DD
= 1.8 V ± 5%, T
j
= 5°–85°C
Impedance
Processor Bus
L3 Bus
Unit
Z
0
Typical
33–42
34–42
Maximum
31–51
32–44
OV
DD
OGND
R
P
R
N
Pad
Data
SW1
SW2
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