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參數(shù)資料
| 型號： | MPC7457EC |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 40/68頁 |
| 文件大?。?/td> | 1755K |
| 代理商： | MPC7457EC |
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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
40
Freescale Semiconductor
Pinout Listings
TDI
E4
High
Input
BVSEL
7
TDO
H1
High
Output
BVSEL
TEA
T1
Low
Input
BVSEL
TEST[0:5]
B10, H6, H10, D8, F9, F8
—
Input
BVSEL
13
TEST[6]
A9
—
Input
BVSEL
10
TMS
K4
High
Input
BVSEL
7
TRST
C1
Low
Input
BVSEL
7, 16
TS
P5
Low
I/O
BVSEL
3
TSIZ[0:2]
L1,H3,D1
High
Output
BVSEL
TT[0:4]
F1, F4, K8, A5, E1
High
I/O
BVSEL
WT
L2
Low
Output
BVSEL
3
V
DD
J9, J11, J13, J15, K10, K12, K14, L9, L11, L13, L15,
M10, M12, M14, N9, N11, N13, N15, P10, P12, P14
—
—
N/A
VDD_SENSE[0:1]
G11, J8
—
—
N/A
17
Notes:
1.
OV
DD
supplies power to the processor bus, JTAG, and all control signals except the L3 cache controls (L3CTL[0:1]); GV
DD
supplies power to the L3 cache interface (L3ADDR[0:17], L3DATA[0:63], L3DP[0:7], L3_ECHO_CLK[0:3], and
L3_CLK[0:1]) and the L3 control signals L3_CNTL[0:1]; and V
DD
supplies power to the processor core and the PLL (after
filtering to become AV
DD
). For actual recommended value of V
in
or supply voltages, see
Table 4
.
Unused address pins must be pulled down to GND.
These pins require weak pull-up resistors (for example, 4.7 k
) to maintain the control signals in the negated state after
they have been actively negated and released by the MPC7457 and other bus masters.
This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going
high.
This signal must be negated during reset, by pull up to OV
DD
or negation by HRESET (inverse of HRESET), to ensure
proper operation.
See
Table 3
for bus voltage configuration information. If used, pull-down resistors should be less than 250
.
Internal pull up on die.
Ignored in 60x bus mode.
These signals must be pulled down to GND if unused or if the MPC7457 is in 60x bus mode.
10. These input signals for factory use only and must be pulled down to GND for normal machine operation.
11. Power must be supplied to GV
DD
, even when the L3 interface is disabled or unused.
12. This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect performance.
13. These input signals are for factory use only and must be pulled up to OV
DD
for normal machine operation.
14. These signals are for factory use only and must be left unconnected for normal machine operation.
15. This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
16. This signal must be asserted during reset, by pull down to GND or assertion by HRESET, to ensure proper operation.
17. These pins are internally connected to V
DD
. They are intended to allow an external device to detect the core voltage level
present at the processor core. If unused, they must be connected directly to V
DD
or left unconnected.
2.
3.
4.
5.
6.
7.
8.
9.
Table 17. Pinout Listing for the MPC7457, 483 CBGA Package (continued)
Signal Name
Pin Number
Active
I/O
I/F Select
1
Notes
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