![](http://datasheet.mmic.net.cn/30000/MQ83C154DXXX-25-883R_datasheet_2377229/MQ83C154DXXX-25-883R_209.png)
209
6384E–ATARM–05-Feb-10
AT91SAM9G20
22.5.4
SDRAM Controller Refresh Cycles
An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are gener-
ated internally by the SDRAM device and incremented after each auto-refresh automatically.
The SDRAM Controller generates these auto-refresh commands periodically. An internal timer is
loaded with the value in the register SDRAMC_TR that indicates the number of clock cycles
between refresh cycles.
A refresh error interrupt is generated when the previous auto-refresh command did not perform.
It is acknowledged by reading the Interrupt Status Register (SDRAMC_ISR).
When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses
are not delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the
device is busy and the master is held by a wait signal. See
Figure 22-5.Figure 22-5. Refresh Cycle Followed by a Read Access
22.5.5
Power Management
Three low-power modes are available:
Self-refresh Mode: The SDRAM executes its own Auto-refresh cycle without control of the
SDRAM Controller. Current drained by the SDRAM is very low.
Power-down Mode: Auto-refresh cycles are controlled by the SDRAM Controller. Between
auto-refresh cycles, the SDRAM is in power-down. Current drained in Power-down mode is
higher than in Self-refresh Mode.
Deep Power-down Mode: (Only available with Mobile SDRAM) The SDRAM contents are
lost, but the SDRAM does not drain any current.
The SDRAM Controller activates one low-power mode as soon as the SDRAM device is not
selected. It is possible to delay the entry in self-refresh and power-down mode after the last
access by programming a timeout value in the Low Power Register.
SDCK
SDCS
RAS
CAS
SDRAMC_A[12:0]
D[31:0]
(input)
tRP = 3
SDWE
Dnb
Dnc
Dnd
col c
col d
CAS = 2
Row m
col a
tRC = 8
tRCD = 3
Dma
Row n