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型號(hào)：	MQ83C154XXX-12P883
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44
封裝：	CERAMIC, QFP-44
文件頁(yè)數(shù)：	467/832頁(yè)
文件大?。?/td>	12467K
代理商：	MQ83C154XXX-12P883

6384E–ATARM–05-Feb-10

AT91SAM9G20

Pin Name List

Product Dependencies

I/O Lines

The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.

Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC

receiver I/O lines to the SSC peripheral mode.

Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC

transmitter I/O lines to the SSC peripheral mode.

Power Management

The SSC is not continuously clocked. The SSC interface may be clocked through the Power

Management Controller (PMC), therefore the programmer must first configure the PMC to

enable the SSC clock.

Interrupt

The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).

Handling interrupts requires programming the AIC before configuring the SSC.

All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each

pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt ser-

vice routine can get the interrupt origin by reading the SSC interrupt status register.

Functional Description

This chapter contains the functional description of the following: SSC Functional Block, Clock

Management, Data format, Start, Transmitter, Receiver and Frame Sync.

The receiver and transmitter operate separately. However, they can work synchronously by pro-

gramming the receiver to use the transmit clock and/or to start a data transfer when transmission

starts. Alternatively, this can be done by programming the transmitter to use the receive clock

and/or to start a data transfer when reception starts. The transmitter and the receiver can be pro-

grammed to operate with the clock signals provided on either the TK or RK pins. This allows the

SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK

and RK pins is the master clock divided by 2.

Table 33-1.

I/O Lines Description

Pin Name

Pin Description

Receiver Frame Synchro

Input/Output

Receiver Clock

Input/Output

Receiver Data

Transmitter Frame Synchro

Input/Output

Transmitter Clock

Input/Output

Transmitter Data

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