![](http://datasheet.mmic.net.cn/30000/MQ83C154DXXX-25-883R_datasheet_2377229/MQ83C154DXXX-25-883R_792.png)
792
6384E–ATARM–05-Feb-10
AT91SAM9G20
Notes:
1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or 5 or 7
(Receive Start Selection), two periods of the MCK must be added to timings.
2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the TK (or
RK) edge and the signal change. The Max access timing is the time between the TK edge and the signal stabilization.
Figure41-20 illustrates Min and Max accesses for SSC0. The same appliess for SSC1, SSC4, and SSC7, SSC10 and SSC13.
Table 41-41. SSC Timings
Symbol
Parameter
Conditions
Min
Max
Units
Transmitter
SSC0
TK edge to TF/TD (TK output, TF output)
MAX corner, VDDIO = 1.8V
ns
MAX corner, VDDIO = 3.3V
ns
SSC
1
TK edge to TF/TD (TK input, TF output)
MAX corner, VDDIO = 1.8V
ns
MAX corner, VDDIO = 3.3V
ns
SSC
2
TF setup time before TK edge (TK output)
MAX corner, VDDIO = 1.8V
21.2 - tCPMCK
ns
MAX corner, VDDIO = 3.3V
15.5 - tCPMCK
ns
SSC
3
TF hold time after TK edge (TK output)
MAX corner, VDDIO = 1.8V
tCPMCK - 13.4
ns
MAX corner, VDDIO = 3.3V
tCPMCK - 9.5
ns
SSC
4
TK edge to TF/TD (TK output, TF input)
MAX corner, VDDIO = 1.8V
2 * tCPMCK +
ns
MAX corner, VDDIO = 3.3V
2 * tCPMCK +
ns
SSC5
TF setup time before TK edge (TK input)
MAX corner, VDDIO = 1.8V
7.4 - t
CPMCK
ns
MAX corner, VDDIO = 3.3V
6.0 - t
CPMCK
ns
SSC6
TF hold time after TK edge (TK input)
MAX corner, VDDIO = 1.8V
t
CPMCK - 0.7
ns
MAX corner, VDDIO = 3.3V
t
CPMCK - 2.0
ns
SSC
7
TK edge to TF/TD (TK input, TF input)
MAX corner, VDDIO = 1.8V
3 * t
CPMCK +
ns
MAX corner, VDDIO = 3.3V
3 * tCPMCK +
ns
Receiver
SSC8
RF/RD setup time before RK edge (RK input)
MAX corner, VDDIO = 1.8V
7.4 - t
CPMCK
ns
MAX corner, VDDIO = 3.3V
6.2 - t
CPMCK
ns
SSC9
RF/RD hold time after RK edge (RK input)
MAX corner, VDDIO = 1.8V
t
CPMCK +7.4
ns
MAX corner, VDDIO = 3.3V
t
CPMCK +6.1
ns
SSC10
RK edge to RF (RK input)
MAX corner, VDDIO = 1.8V
ns
MAX corner, VDDIO = 3.3V
ns
SSC11
RF/RD setup time before RK edge (RK output)
MAX corner, VDDIO = 1.8V
21.6 - t
CPMCK
ns
MAX corner, VDDIO = 3.3V
15.9 - t
CPMCK
ns
SSC12
RF/RD hold time after RK edge (RK output)
MAX corner, VDDIO = 1.8V
t
CPMCK - 10.5
ns
MAX corner, VDDIO = 3.3V
t
CPMCK - 6.5
ns
SSC13
RK edge to RF (RK output)
MAX corner, VDDIO = 1.8V
ns
MAX corner, VDDIO = 3.3V
ns