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型號：	MQ83C154XXX-12P883
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44
封裝：	CERAMIC, QFP-44
文件頁數(shù)：	133/832頁
文件大?。?/td>	12467K
代理商：	MQ83C154XXX-12P883

6384E–ATARM–05-Feb-10

AT91SAM9G20

SDRAMC Low Power Register

Register Name:SDRAMC_LPR

Access Type:Read-write

Reset Value:0x0

LPCB: Low-power Configuration Bits

PASR: Partial Array Self-refresh (only for low-power SDRAM)

PASR parameter is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks

of the SDRAM array are enabled. Disabled banks are not refreshed in self-refresh mode. This parameter must be set

according to the SDRAM device specification.

TCSR: Temperature Compensated Self-Refresh (only for low-power SDRAM)

TCSR parameter is transmitted to the SDRAM during initialization to set the refresh interval during self-refresh mode

depending on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device

specification.

DS: Drive Strength (only for low-power SDRAM)

DS parameter is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parame-

ter must be set according to the SDRAM device specification.

Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM

The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCLK clock is deactivated and the

SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the

The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is

set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access.

The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to low-

power SDRAM.

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