![](http://datasheet.mmic.net.cn/30000/MQ83C154DXXX-25-883R_datasheet_2377229/MQ83C154DXXX-25-883R_645.png)
645
6384E–ATARM–05-Feb-10
AT91SAM9G20
36.5.4
Transmit Status Register
Register Name:
EMAC_TSR
Access Type:
Read-write
This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1
to them. It is not possible to set a bit to 1 by writing to the register.
UBR: Used Bit Read
Set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit.
COL: Collision Occurred
Set by the assertion of collision. Cleared by writing a one to this bit.
RLE: Retry Limit exceeded
Cleared by writing a one to this bit.
TGO: Transmit Go
If high transmit is active.
BEX: Buffers exhausted mid frame
If the buffers run out during transmission of a frame, then transmission stops, FCS shall be bad and tx_er asserted. Cleared
by writing a one to this bit.
COMP: Transmit Complete
Set when a frame has been transmitted. Cleared by writing a one to this bit.
UND: Transmit Underrun
Set when transmit DMA was not able to read data from memory, either because the bus was not granted in time, because
a not OK hresp(bus error) was returned or because a used bit was read midway through frame transmission. If this
occurs, the transmitter forces bad CRC. Cleared by writing a one to this bit.
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UND
COMP
BEX
TGO
RLE
COL
UBR