參數(shù)資料
型號(hào)： MSC7119VM1200
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 0-BIT, 300 MHz, OTHER DSP, PBGA400
封裝： LEAD FREE, MAPBGA-400
文件頁(yè)數(shù)： 13/60頁(yè)
文件大?。?/td> 1138K
代理商： MSC7119VM1200
MSC7119 Data Sheet, Rev. 8
Electrical Characteristics
Freescale Semiconductor
20
Table 6 lists the DDR DRAM capacitance.
Tri-state (high impedance off state) leakage current,
VIN = VDDIO
IOZ
–1.0
0.09
1
A
Signal low input current, VIL = 0.4 V
IL
–1.0
0.09
1
A
Signal high input current, VIH = 2.0 V
IH
–1.0
0.09
1
A
Output high voltage, IOH = –2 mA, except open drain pins
VOH
2.0
3.0
—
V
Output low voltage, IOL= 5 mA
VOL
—0
0.4
V
Typical power at 300 MHz5
P
—
324.0
—
mW
Notes:
1.
The value of VDDM at the MSC7119 device must remain within 50 mV of VDDM at the DRAM device at all times.
2.
VREF must be equal to 50% of VDDM and track VDDM variations as measured at the receiver. Peak-to-peak noise must not
exceed ±2% of the DC value.
3.
VTT is not applied directly to the MSC7119 device. It is the level measured at the far end signal termination. It should be equal
to VREF. This rail should track variations in the DC level of VREF.
4.
Output leakage for the memory interface is measured with all outputs disabled, 0 V
≤ VOUT ≤ VDDM.
5.
The core power values were measured.using a standard EFR pattern at typical conditions (25°C, 300 MHz, 1.2 V core).
Table 6. DDR DRAM Capacitance
Parameter/Condition
Symbol
Max
Unit
Input/output capacitance: DQ, DQS
CIO
30
pF
Delta input/output capacitance: DQ, DQS
CDIO
30
pF
Note:
These values were measured under the following conditions:
VDDM = 2.5 V ± 0.125 V
f = 1 MHz
TA = 25°C
VOUT = VDDM/2
VOUT (peak to peak) = 0.2 V
Table 5. DC Electrical Characteristics (continued)
Characteristic
Symbol
Min
Typical
Max
Unit
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