參數(shù)資料
型號: MSC7119VM1200
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 300 MHz, OTHER DSP, PBGA400
封裝: LEAD FREE, MAPBGA-400
文件頁數(shù): 33/60頁
文件大?。?/td> 1138K
代理商: MSC7119VM1200
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
39
2.5.13
JTAG Signals
Table 31. JTAG Timing
No.
Characteristics
All frequencies
Unit
Min
Max
700
TCK frequency of operation (1/(T
C ×
3)
Note:
TC = 1/CLOCK which is the period of the core clock. The TCK
frequency must less than 1/3 of the core frequency with an absolute
maximum limit of 40 MHz.
0.0
40.0
MHz
701
TCK cycle time
25.0
ns
702
TCK clock pulse width measured at VM = 1.6 V
11.0
ns
703
TCK rise and fall times
0.0
3.0
ns
704
Boundary scan input data set-up time
5.0
ns
705
Boundary scan input data hold time
14.0
ns
706
TCK low to output data valid
0.0
20.0
ns
707
TCK low to output high impedance
0.0
20.0
ns
708
TMS, TDI data set-up time
5.0
ns
709
TMS, TDI data hold time
14.0
ns
710
TCK low to TDO data valid
0.0
24.0
ns
711
TCK low to TDO high impedance
0.0
10.0
ns
712
TRST assert time
100.0
ns
Note:
All timings apply to OCE module data transfers as the OCE module uses the JTAG port as an interface.
Figure 26. Test Clock Input Timing Diagram
TCK
(Input)
VM
VIH
VIL
701
702
703
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