參數(shù)資料
型號(hào): MSC7119VM1200
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 0-BIT, 300 MHz, OTHER DSP, PBGA400
封裝: LEAD FREE, MAPBGA-400
文件頁(yè)數(shù): 47/60頁(yè)
文件大?。?/td> 1138K
代理商: MSC7119VM1200
Hardware Design Considerations
MSC7119 Data Sheet, Rev. 8
Freescale Semiconductor
51
3.3.6
Example Total Power Consumption
Using the examples in this section and assuming four peripherals and 10 I/O lines active, a total power consumption value is
estimated as the following:
PTOTAL = 324.0 + (4 × 4.32) + 326.3 + (10 × 5.44) + 64 = 784.98 mW
Eqn. 13
3.4
Reset and Boot
This section describes the recommendations for configuring the MSC7119 at reset and boot.
3.4.1
Reset Circuit
HRESET
is a bidirectional signal and, if driven as an input, should be driven with an open collector or open-drain device. For
an open-drain output such as HRESET, take care when driving many buffers that implement input bus-hold circuitry. The
bus-hold currents can cause enough voltage drop across the pull-up resistor to change the logic level to low. Either a smaller
value of pull-up or less current loading from the bus-hold drivers overcomes this issue. To avoid exceeding the MSC7119 output
current, the pull-up value should not be too small (a 1 K
Ω pull-up resistor is used in the MSC711xADS reference design).
3.4.2
Reset Configuration Pins
Table 34 shows the MSC7119 reset configuration signals. These signals are sampled at the deassertion (rising edge) of
PORESET
. For details, refer to the Reset chapter of the MSC711x Reference Manual.
Table 34. Reset Configuration Signals
Signal
Description
Settings
BM[3–0]
Determines boot mode.
See Table 35 for details.
SWTE
Determines watchdog functionality.
0
Watchdog timer disabled.
1
Watchdog timer enabled.
HDSP
Configures HDI16 strobe polarity.
0
Host Data strobes active low.
1
Host Data strobes active high.
H8BIT
Configures HDI16 operation mode.
0
HDI16 port configured for 16-bit operation.
1
HDI16 port configured for 8-bit operation.
相關(guān)PDF資料
PDF描述
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